Noesis

Hardware

Silicon to signal — transistors, boards, embedded systems.

notes
334notes
chapters
24chapters
tests
126tests
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0.7Mwords
Test bank →Learning path →Deep dives → (293 topics)

Phase 1 — Electrical & Physical Foundations

Absolute beginner • 4–6 weeks3 chapters
1.1

Electricity & Charge Basics

14 topics
  1. 1.1.1Define electric charge, electron, proton, and the coulomb
  2. 1.1.2Understand conductors, insulators, and semiconductors
  3. 1.1.3Define voltage (potential difference) and its units
  4. 1.1.4Define current (flow of charge) and the ampere
  5. 1.1.5Define resistance and the ohm
  6. 1.1.6State and apply Ohm's Law (V = IR)
  7. 1.1.7Calculate electrical power (P = VI, P = I²R)
  8. 1.1.8Distinguish DC vs AC signals
  9. 1.1.9Understand conventional current vs electron flow direction
  10. 1.1.10Define electric field and electric potential
  11. 1.1.11Understand capacitance and the farad
  12. 1.1.12Understand inductance and the henry
  13. 1.1.13Define energy (joules) vs power (watts)
  14. 1.1.14Read and interpret circuit schematic symbols
1.2

Circuit Analysis Fundamentals

14 topics
  1. 1.2.1Series vs parallel resistor combinations
  2. 1.2.2Compute equivalent resistance in mixed networks
  3. 1.2.3Apply Kirchhoff's Current Law (KCL)
  4. 1.2.4Apply Kirchhoff's Voltage Law (KVL)
  5. 1.2.5Build and analyze a voltage divider
  6. 1.2.6Build and analyze a current divider
  7. 1.2.7Understand RC charging - discharging time constants
  8. 1.2.8Understand RL transient behavior
  9. 1.2.9Use Thevenin equivalent circuits
  10. 1.2.10Use Norton equivalent circuits
  11. 1.2.11Apply superposition theorem
  12. 1.2.12Read multimeter measurements (V, I, R)
  13. 1.2.13Understand grounding and reference nodes
  14. 1.2.14Analyze simple AC circuits with reactance
1.3

Materials & Atomic Structure

10 topics
  1. 1.3.1Bohr atomic model and electron shells
  2. 1.3.2Valence electrons and bonding
  3. 1.3.3Covalent bonding in silicon crystals
  4. 1.3.4Crystal lattice structure of silicon
  5. 1.3.5Intrinsic vs extrinsic semiconductors
  6. 1.3.6Electron-hole pair generation
  7. 1.3.7Concept of carrier mobility
  8. 1.3.8Thermal effects on conductivity
  9. 1.3.9Why silicon dominates over germanium
  10. 1.3.10Compound semiconductors (GaN, GaAs, SiC) overview

Phase 2 — Semiconductor Physics & Devices

Beginner→Intermediate • 6–8 weeks4 chapters
2.1

Band Theory & Carrier Physics

13 topics
  1. 2.1.1Energy bands - valence band and conduction band
  2. 2.1.2Band gap and its meaning for conductivity
  3. 2.1.3Compare band gaps - conductor - semiconductor - insulator
  4. 2.1.4Fermi level and Fermi-Dirac distribution
  5. 2.1.5Direct vs indirect band gap materials
  6. 2.1.6Carrier concentration equations (n, p, ni)
  7. 2.1.7Mass action law (np = ni²)
  8. 2.1.8Drift current and electric field
  9. 2.1.9Diffusion current and concentration gradient
  10. 2.1.10Einstein relation between mobility and diffusion
  11. 2.1.11Recombination and generation mechanisms
  12. 2.1.12Minority vs majority carriers
  13. 2.1.13Temperature dependence of carrier concentration
2.2

Doping & PN Junctions

13 topics
  1. 2.2.1N-type doping with donor atoms (phosphorus, arsenic)
  2. 2.2.2P-type doping with acceptor atoms (boron)
  3. 2.2.3Donor - acceptor energy levels in the band gap
  4. 2.2.4Formation of a PN junction
  5. 2.2.5Depletion region and space charge
  6. 2.2.6Built-in potential of a junction
  7. 2.2.7Forward bias behavior
  8. 2.2.8Reverse bias behavior
  9. 2.2.9Diode I-V characteristic curve
  10. 2.2.10Shockley diode equation
  11. 2.2.11Junction capacitance (depletion + diffusion)
  12. 2.2.12Reverse breakdown - avalanche vs Zener
  13. 2.2.13Reverse saturation current
2.3

Diodes & Applications

10 topics
  1. 2.3.1Rectifier diodes and half-wave rectification
  2. 2.3.2Full-wave and bridge rectifiers
  3. 2.3.3Zener diodes for voltage regulation
  4. 2.3.4Light-emitting diodes (LED) operation
  5. 2.3.5Photodiodes and solar cells
  6. 2.3.6Schottky diodes and metal-semiconductor junctions
  7. 2.3.7Varactor diodes
  8. 2.3.8Diode clipping and clamping circuits
  9. 2.3.9Diode logic gate basics
  10. 2.3.10Datasheet parameters (Vf, Ir, max ratings)
2.4

Chapter 2.4

17 topics
  1. 2.4.1BJT structure (NPN and PNP)
  2. 2.4.2BJT operating regions (cutoff, active, saturation)
  3. 2.4.3Current gain β (hFE) and α
  4. 2.4.4BJT as a switch
  5. 2.4.5BJT as an amplifier (common emitter)
  6. 2.4.6BJT biasing techniques
  7. 2.4.7JFET structure and operation
  8. 2.4.8MOSFET structure (gate, source, drain, body)
  9. 2.4.9Enhancement vs depletion mode MOSFETs
  10. 2.4.10NMOS vs PMOS
  11. 2.4.11Threshold voltage (Vth)
  12. 2.4.12MOSFET I-V curves (triode and saturation)
  13. 2.4.13Transconductance (gm)
  14. 2.4.14MOSFET as a switch
  15. 2.4.15Channel length and short-channel effects
  16. 2.4.16Body effect and substrate bias
  17. 2.4.17Subthreshold leakage current

Phase 3 — Digital Logic & Circuit Design

Intermediate • 6–8 weeks5 chapters
3.1

Boolean Algebra & Logic Gates

15 topics
  1. 3.1.1Binary number system and bit - byte concepts
  2. 3.1.2Hexadecimal and octal representation
  3. 3.1.3Two's complement signed numbers
  4. 3.1.4Boolean variables and operations (AND, OR, NOT)
  5. 3.1.5Truth tables construction
  6. 3.1.6XOR, NAND, NOR, XNOR gates
  7. 3.1.7Boolean algebra laws (commutative, associative, distributive)
  8. 3.1.8De Morgan's theorems
  9. 3.1.9Sum of products (SOP) form
  10. 3.1.10Product of sums (POS) form
  11. 3.1.11Karnaugh map simplification (2,3,4 variables)
  12. 3.1.12Don't-care conditions in K-maps
  13. 3.1.13Quine-McCluskey method
  14. 3.1.14Universal gates (NAND - NOR completeness)
  15. 3.1.15Logic gate propagation delay
3.2

CMOS Circuit Design

13 topics
  1. 3.2.1CMOS inverter structure and operation
  2. 3.2.2Pull-up and pull-down networks
  3. 3.2.3CMOS NAND and NOR gate design
  4. 3.2.4Static vs dynamic power dissipation
  5. 3.2.5Voltage transfer characteristic (VTC)
  6. 3.2.6Noise margins (NMH, NML)
  7. 3.2.7Propagation delay and rise - fall times
  8. 3.2.8Fan-in and fan-out limits
  9. 3.2.9Transmission gates
  10. 3.2.10Pass-transistor logic
  11. 3.2.11Dynamic CMOS logic
  12. 3.2.12Domino logic
  13. 3.2.13Power-delay product
3.3

Combinational Circuits

14 topics
  1. 3.3.1Half adder and full adder
  2. 3.3.2Ripple-carry adder
  3. 3.3.3Carry-lookahead adder
  4. 3.3.4Subtractors
  5. 3.3.5Multiplexers (2 - 1, 4 - 1, n - 1)
  6. 3.3.6Demultiplexers
  7. 3.3.7Encoders and priority encoders
  8. 3.3.8Decoders (2 - 4, 3 - 8)
  9. 3.3.9Comparators
  10. 3.3.10Parity generators - checkers
  11. 3.3.11Barrel shifters
  12. 3.3.12Combinational multipliers
  13. 3.3.13ALU design fundamentals
  14. 3.3.14Hazards (static and dynamic) in combinational logic
3.4

Sequential Circuits

15 topics
  1. 3.4.1SR latch operation
  2. 3.4.2D latch and gated latches
  3. 3.4.3Edge-triggered D flip-flop
  4. 3.4.4JK and T flip-flops
  5. 3.4.5Setup and hold time constraints
  6. 3.4.6Clock-to-Q delay
  7. 3.4.7Registers and shift registers
  8. 3.4.8Synchronous vs asynchronous counters
  9. 3.4.9Ring and Johnson counters
  10. 3.4.10Finite state machines (Mealy and Moore)
  11. 3.4.11State diagram and state table design
  12. 3.4.12State minimization techniques
  13. 3.4.13Metastability and synchronizers
  14. 3.4.14Clock domain crossing
  15. 3.4.15Clock skew and jitter
3.5

HDL & Digital Design Flow

10 topics
  1. 3.5.1Verilog - VHDL syntax basics
  2. 3.5.2Combinational logic in HDL
  3. 3.5.3Sequential logic and always blocks
  4. 3.5.4Blocking vs non-blocking assignments
  5. 3.5.5Testbenches and simulation
  6. 3.5.6RTL (register transfer level) design
  7. 3.5.7Synthesis to gate-level netlist
  8. 3.5.8FPGA vs ASIC design flow
  9. 3.5.9Timing analysis basics (static timing)
  10. 3.5.10Critical path identification

Phase 4 — Memory, VLSI & Fabrication

Intermediate→Advanced • 6–8 weeks3 chapters
4.1

Memory Technologies

15 topics
  1. 4.1.1SRAM 6T cell structure and operation
  2. 4.1.2SRAM read - write operations
  3. 4.1.3DRAM 1T1C cell structure
  4. 4.1.4DRAM refresh and charge leakage
  5. 4.1.5Row - column addressing and sense amplifiers
  6. 4.1.6SDRAM and DDR (DDR2 - 3 - 4 - 5) evolution
  7. 4.1.7ROM, PROM, EPROM, EEPROM
  8. 4.1.8Flash memory (NOR vs NAND)
  9. 4.1.9Floating gate transistor operation
  10. 4.1.10Multi-level cell (MLC - TLC - QLC) flash
  11. 4.1.11Wear leveling and flash controllers
  12. 4.1.12Emerging memories (MRAM, ReRAM, PCM)
  13. 4.1.13Content-addressable memory (CAM)
  14. 4.1.14Memory bandwidth and latency metrics
  15. 4.1.15ECC and memory error correction
4.2

VLSI Design

15 topics
  1. 4.2.1Moore's Law and scaling trends
  2. 4.2.2Dennard scaling and its breakdown
  3. 4.2.3Full custom vs standard cell design
  4. 4.2.4Standard cell libraries
  5. 4.2.5Place and route (P&R)
  6. 4.2.6Floorplanning and power planning
  7. 4.2.7Clock tree synthesis
  8. 4.2.8Design rule checking (DRC)
  9. 4.2.9Layout vs schematic (LVS)
  10. 4.2.10Parasitic extraction (RC)
  11. 4.2.11Signal integrity and crosstalk
  12. 4.2.12Power grid and IR drop analysis
  13. 4.2.13Design for testability (DFT)
  14. 4.2.14Scan chains and BIST
  15. 4.2.15Low-power design techniques (clock - power gating)
4.3

Semiconductor Fabrication

22 topics
  1. 4.3.1Silicon wafer production (Czochralski process)
  2. 4.3.2Wafer cleaning and preparation
  3. 4.3.3Oxidation (thermal SiO2 growth)
  4. 4.3.4Photolithography process steps
  5. 4.3.5Photoresist (positive and negative)
  6. 4.3.6Masks - reticles and projection systems
  7. 4.3.7Deep UV (DUV) lithography
  8. 4.3.8Extreme UV (EUV) lithography
  9. 4.3.9Multi-patterning techniques
  10. 4.3.10Etching (wet vs dry - plasma)
  11. 4.3.11Ion implantation and diffusion
  12. 4.3.12Chemical vapor deposition (CVD)
  13. 4.3.13Physical vapor deposition (PVD - sputtering)
  14. 4.3.14Atomic layer deposition (ALD)
  15. 4.3.15Chemical mechanical planarization (CMP)
  16. 4.3.16Metallization and interconnect layers
  17. 4.3.17Copper damascene process
  18. 4.3.18Process nodes (28nm→7nm→5nm→3nm→2nm)
  19. 4.3.19FinFET transistor structure
  20. 4.3.20Gate-all-around (GAA) nanosheet transistors
  21. 4.3.21Yield, defect density, and binning
  22. 4.3.22Packaging and wire bonding - flip-chip

Phase 5 — Computer Architecture & Microarchitecture

Advanced • 8–10 weeks4 chapters
5.1

Instruction Set Architecture (ISA)

13 topics
  1. 5.1.1CISC vs RISC philosophies
  2. 5.1.2Instruction formats and encoding
  3. 5.1.3Addressing modes
  4. 5.1.4Register file organization
  5. 5.1.5x86 architecture overview
  6. 5.1.6ARM architecture overview
  7. 5.1.7RISC-V base ISA (RV32I - RV64I)
  8. 5.1.8RISC-V extensions (M, A, F, D, V, C)
  9. 5.1.9Load - store architecture model
  10. 5.1.10Calling conventions and ABI
  11. 5.1.11Endianness (big vs little)
  12. 5.1.12Instruction-level semantics and exceptions
  13. 5.1.13System vs user mode and privilege levels
5.2

Processor Datapath & Pipelining

12 topics
  1. 5.2.1Single-cycle datapath design
  2. 5.2.2Multi-cycle datapath
  3. 5.2.3Classic 5-stage pipeline (IF - ID - EX - MEM - WB)
  4. 5.2.4Pipeline registers and control signals
  5. 5.2.5Structural hazards
  6. 5.2.6Data hazards and forwarding - bypassing
  7. 5.2.7Load-use hazard and stalls
  8. 5.2.8Control hazards and pipeline flushes
  9. 5.2.9Pipeline throughput and CPI
  10. 5.2.10Hazard detection units
  11. 5.2.11Deep pipelining trade-offs
  12. 5.2.12Precise exceptions in pipelines
5.3

Advanced Microarchitecture

15 topics
  1. 5.3.1Superscalar execution
  2. 5.3.2Out-of-order execution
  3. 5.3.3Tomasulo's algorithm
  4. 5.3.4Register renaming
  5. 5.3.5Reorder buffer (ROB)
  6. 5.3.6Reservation stations
  7. 5.3.7Branch prediction (static and dynamic)
  8. 5.3.82-bit saturating counter predictors
  9. 5.3.9Branch target buffer (BTB)
  10. 5.3.10Tournament and TAGE predictors
  11. 5.3.11Speculative execution
  12. 5.3.12Return address stack
  13. 5.3.13VLIW architectures
  14. 5.3.14Simultaneous multithreading (SMT - hyperthreading)
  15. 5.3.15Spectre - Meltdown speculative side channels
5.4

Memory Hierarchy & Caches

17 topics
  1. 5.4.1Principle of locality (temporal - spatial)
  2. 5.4.2Cache organization (direct-mapped)
  3. 5.4.3Set-associative and fully associative caches
  4. 5.4.4Cache line size and tags
  5. 5.4.5Replacement policies (LRU, FIFO, random)
  6. 5.4.6Write-through vs write-back
  7. 5.4.7Write-allocate vs no-allocate
  8. 5.4.8Multi-level cache hierarchy (L1 - L2 - L3)
  9. 5.4.9Cache miss types (compulsory, capacity, conflict)
  10. 5.4.10Average memory access time (AMAT)
  11. 5.4.11Virtual memory and paging
  12. 5.4.12TLB (translation lookaside buffer)
  13. 5.4.13Page tables and multi-level paging
  14. 5.4.14Cache coherence problem
  15. 5.4.15MESI - MOESI coherence protocols
  16. 5.4.16Memory consistency models
  17. 5.4.17Prefetching strategies

Phase 6 — Parallel, GPU & Cutting-Edge Systems

Advanced / Cutting-edge • 8–12 weeks5 chapters
6.1

Parallelism & Multicore

12 topics
  1. 6.1.1Flynn's taxonomy (SISD - SIMD - MIMD)
  2. 6.1.2Instruction-level vs thread-level parallelism
  3. 6.1.3Amdahl's Law and Gustafson's Law
  4. 6.1.4Multicore vs manycore designs
  5. 6.1.5Shared memory vs distributed memory
  6. 6.1.6Cache coherence at scale (directory-based)
  7. 6.1.7NUMA architectures
  8. 6.1.8Synchronization primitives (locks, barriers)
  9. 6.1.9Atomic operations and CAS
  10. 6.1.10False sharing problem
  11. 6.1.11Vector - SIMD instructions (SSE, AVX, NEON)
  12. 6.1.12Heterogeneous computing concepts
6.2

GPU Architecture

15 topics
  1. 6.2.1GPU vs CPU design philosophy
  2. 6.2.2Streaming multiprocessors (SM)
  3. 6.2.3CUDA cores and execution model
  4. 6.2.4SIMT (single instruction multiple thread)
  5. 6.2.5Warps and warp scheduling
  6. 6.2.6Thread blocks and grids
  7. 6.2.7Memory hierarchy (global, shared, registers)
  8. 6.2.8Coalesced memory access
  9. 6.2.9Bank conflicts in shared memory
  10. 6.2.10Occupancy and latency hiding
  11. 6.2.11Warp divergence penalties
  12. 6.2.12Tensor cores and matrix operations
  13. 6.2.13CUDA programming model basics
  14. 6.2.14GPU memory bandwidth optimization
  15. 6.2.15ROCm - OpenCL alternatives
6.3

Interconnects, Buses & SoC

12 topics
  1. 6.3.1Bus topologies and arbitration
  2. 6.3.2PCI Express (PCIe) architecture and generations
  3. 6.3.3PCIe lanes, links, and bandwidth
  4. 6.3.4NVLink and GPU interconnects
  5. 6.3.5CXL (Compute Express Link)
  6. 6.3.6Network-on-Chip (NoC) topologies
  7. 6.3.7AXI - AMBA on-chip protocols
  8. 6.3.8DMA controllers
  9. 6.3.9System-on-Chip (SoC) integration
  10. 6.3.10IP cores and SoC bus fabric
  11. 6.3.11Infinity Fabric - mesh interconnects
  12. 6.3.12Serial vs parallel signaling (SerDes)
6.4

Power, Thermal & Reliability

10 topics
  1. 6.4.1Dynamic vs static power consumption
  2. 6.4.2Dynamic voltage and frequency scaling (DVFS)
  3. 6.4.3Thermal design power (TDP)
  4. 6.4.4Power gating and clock gating
  5. 6.4.5Heat dissipation and cooling solutions
  6. 6.4.6Thermal throttling mechanisms
  7. 6.4.7Dark silicon problem
  8. 6.4.8Electromigration reliability
  9. 6.4.9Voltage droop and decoupling capacitors
  10. 6.4.10Energy efficiency (performance per watt)
6.5

Advanced & Emerging Architectures

18 topics
  1. 6.5.1Chiplets and multi-die integration
  2. 6.5.22.5D packaging and interposers
  3. 6.5.33D stacking and through-silicon vias (TSV)
  4. 6.5.4High Bandwidth Memory (HBM - HBM2 - HBM3)
  5. 6.5.5Processing-in-memory (PIM)
  6. 6.5.6Domain-specific accelerators
  7. 6.5.7Google TPU architecture and systolic arrays
  8. 6.5.8Neural processing units (NPUs)
  9. 6.5.9Dataflow architectures
  10. 6.5.10FPGA-based acceleration
  11. 6.5.11RISC-V custom extensions for accelerators
  12. 6.5.12Open hardware ecosystem (OpenRISC, OpenTitan)
  13. 6.5.13Quantum computing hardware basics
  14. 6.5.14Neuromorphic computing
  15. 6.5.15Photonic and optical interconnects
  16. 6.5.16Approximate computing techniques
  17. 6.5.17Wafer-scale engines (Cerebras-style)
  18. 6.5.18Co-packaged optics trends