This is the crux — and where the sequential model earns its keep.
HOW is this achieved in a pipeline? Instructions may compute out of order or speculatively, but they
commit (retire, becoming visible) strictly in program order. When an exception is detected, the
hardware:
Marks the offending instruction.
Squashes (discards) it and everything younger — their results never reach architectural state.
Lets everything older commit.
Saves the Exception PC (EPC) and cause, then jumps to the vector.
Imagine a chef following a recipe, one step at a time. Someone watching only sees the finished dish after
each step — that's the architectural state. The chef might secretly prep two steps at once to save time,
but the watcher must never notice; the dish must look exactly as if steps were done in order.
Now suppose a step says "add the eggs" but the eggs are still in the fridge. The chef freezes, undoes any
half-done later steps, and calls the manager (the OS): "get the eggs!" That freeze-and-call is an exception.
Once eggs arrive, the chef re-does that same step. If instead the recipe just said "ring a bell for the
customer" (a trap), the chef finishes and simply moves to the next step. The trick: always leave the kitchen
looking clean at a step boundary so anyone can take over.
What is instruction-level (architectural) semantics?
The ISA guarantee that instructions appear to execute atomically, one at a time, in program order, transforming the visible architectural state.
Architectural vs microarchitectural state?
Architectural = programmer-visible (registers, PC, flags, memory) and defined by the ISA; microarchitectural = implementation detail (pipeline latches, caches, ROB) invisible to software.
Give the state-transition form of an instruction.
state_{n+1} = execute(instr, state_n).
Why does default PC update = PC+4?
In a fixed-length ISA each instruction is 4 bytes, so the next instruction is 4 bytes ahead; updating PC is part of the instruction's meaning.
Define an exception.
An unexpected, control-transferring event detected during execution that the running program can't handle, sending control to an OS handler at a vector address.
Fault vs Trap: where does the handler return?
Fault → same (faulting) instruction; Trap → the next instruction.
Exception = synchronous (caused by the instruction stream, reproducible); Interrupt = asynchronous (external device, timing-dependent).
Define a precise exception.
When the handler starts, all older instructions have fully committed and the faulting instruction plus all younger ones have modified no architectural state.
Why do we need precise exceptions?
So the OS can inspect a clean single-instruction boundary, fix the cause, and cleanly restart the program.
How does an out-of-order pipeline stay precise?
Instructions execute out of order but commit/retire in program order; on a fault, younger instructions are squashed before affecting architectural state.
If two instructions fault in the same cycle, which is reported?
The oldest (earliest in program order), preserving the sequential model.
On a page fault during LW, is the destination register written?
No — precise semantics requires the faulting instruction to leave architectural state unchanged so it can be retried.
What is the EPC?
The Exception PC: saved address used to return from the handler (faulting instruction for faults, next instruction for traps).
Dekho, CPU ka ek promise hota hai: instructions ko ek-ek karke, program order mein, poora complete
karke chalana. Isko hum instruction-level (architectural) semantics kehte hain. Andar-andar
hardware bahut smart hai — pipelining, out-of-order, speculation sab karta hai — par bahar se
visible state (registers, PC, memory) hamesha aisa dikhna chahiye jaise sab kuch strictly ek line
mein hua ho. Yahi contract hai software aur hardware ke beech; isi wajah se company processor ka
andar redesign kar sakti hai bina tumhara program toda.
Ab exception kya hai? Jab koi instruction normally complete nahi kar sakta — jaise page memory
mein nahi hai (page fault), ya divide-by-zero — tab hardware control ko OS ke handler ko de deta
hai. Teen type yaad rakho: Fault (theek ho sakta hai, wahi instruction dobara chalao — jaise page
fault), Trap (jaan-boojh kar, kaam ho gaya, agli instruction se continue — jaise syscall), aur
Abort (hardware kharab, recover nahi hota). Sabse bada confusion: fault ke baad same instruction
pe wapas aana, trap ke baad next pe. Yeh EPC (return PC) decide karta hai.
Sabse important concept hai precise exception. Matlab jab handler start ho, to faulting instruction
se pehle wale sab poore ho chuke hon, aur woh instruction aur uske baad wale ne architectural state ko
bilkul touch na kiya ho. Isse OS clean point pe program ko fix karke restart kar sakta hai. Out-of-order
CPU mein bhi yeh possible hai kyunki instructions commit hamesha in-order hoti hain — fault detect
hote hi younger instructions ko squash (discard) kar dete hain. Aur agar do exception ek saath aayein,
to oldest wali report hoti hai, kyunki sequential model yahi kehta hai. Bas yeh do line yaad rakho:
"Fault = fix and re-fire same instruction, Trap = task done, travel on."