Level 1 — RecognitionInstruction Set Architecture (ISA)

Instruction Set Architecture (ISA)

⏱ 20 minutes30 marksprintable — key stays hidden on paper

Time limit: 20 minutes Total marks: 30

Section A — Multiple Choice (1 mark each)

Choose the single best answer.

Q1. Which characteristic is most associated with a RISC philosophy rather than CISC?

(a) Variable-length instructions with many addressing modes
(b) Fixed-length instructions and a load/store model
(c) Microcoded complex instructions
(d) Memory-to-memory arithmetic operations

Q2. In a load/store architecture, arithmetic instructions operate on:

(a) Memory operands directly
(b) Only immediate operands
(c) Registers (and immediates) only
(d) I/O ports

Q3. In RISC-V RV32I, an R-type instruction encodes which fields?

(a) opcode, rd, funct3, rs1, rs2, funct7
(b) opcode, rd, imm[31:12]
(c) opcode, rs1, rs2, imm[11:0]
(d) opcode only

Q4. The addressing mode that computes the operand address as Register + constant offset is called:

(a) Immediate
(b) Register direct
(c) Base-plus-displacement (register indirect with offset)
(d) PC-relative absolute

Q5. In a little-endian system, the 32-bit value 0x12345678 stored at address 0x100 has which byte at address 0x100?

(a) 0x12
(b) 0x34
(c) 0x56
(d) 0x78

Q6. Which RISC-V standard extension provides integer multiply and divide?

(a) A
(b) M
(c) F
(d) C

Q7. A trap that transfers control to a handler running in a higher privilege level is typically caused by all EXCEPT:

(a) A system call (ecall)
(b) A page fault
(c) An ordinary register-to-register add with no error
(d) An illegal instruction

Q8. The purpose of a calling convention / ABI is primarily to:

(a) Define the clock frequency of the CPU
(b) Standardize register usage, argument passing, and stack layout across functions
(c) Encrypt the instruction stream
(d) Select big- vs little-endian at runtime

Q9. In RV32I, how many bits are used to name one of the 32 integer registers?

(a) 3
(b) 4
(c) 5
(d) 6

Q10. User mode differs from supervisor/machine mode primarily in that user mode:

(a) Runs faster
(b) Cannot execute certain privileged instructions or access protected resources
(c) Uses a different endianness
(d) Has more general-purpose registers

Section B — Matching (1 mark each, 5 marks total)

Q11. Match each item in Column X to the best description in Column Y. Write pairs (e.g. 1→c).

Column X	Column Y
1. ARM	a. Open, free RISC ISA with modular extensions
2. x86	b. RISC ISA widely used in mobile/embedded devices
3. RISC-V	c. Dominant CISC ISA in desktops/servers, variable-length instructions
4. I-type (RV32I)	d. Immediate encoded in bits [31:20], used by loads and `addi`
5. Register file	e. Small, fast bank of named storage inside the CPU

Section C — True/False with Justification (2 marks each: 1 for T/F, 1 for justification)

Q12. In a pure load/store architecture, add [mem1], [mem2] (memory-to-memory add) is a valid single instruction.

Q13. The x0 register in RISC-V is hardwired to zero and writes to it are discarded.

Q14. Big-endian and little-endian systems store the same byte values in memory but in reversed byte order for multi-byte scalars.

Q15. CISC instructions are always faster than RISC instructions because one CISC instruction can do more work.

Q16. PC-relative addressing helps produce position-independent code because branch/jump targets are expressed as offsets from the current instruction.

Q17. An ecall/system-call instruction executed in user mode raises an exception that lets privileged software service the request.

Q18. A fixed 32-bit instruction width guarantees that every instruction can encode an arbitrary 32-bit immediate directly.

Answer keyMark scheme & solutions

Section A (1 mark each)

Q1 → (b). RISC = fixed-length instructions + load/store model. Variable length, microcode, and memory-to-memory ops are CISC traits.

Q2 → (c). Load/store ISAs restrict ALU ops to registers/immediates; memory is touched only by explicit load/store.

Q3 → (a). R-type layout: funct7 | rs2 | rs1 | funct3 | rd | opcode. It has two source registers, a destination, and function fields — no immediate.

Q4 → (c). Base-plus-displacement computes effective address = base register + signed offset. This is exactly RISC-V's lw rd, offset(rs1).

Q5 → (d). Little-endian stores the least-significant byte at the lowest address, so byte 0x78 sits at 0x100. (Order: 78, 56, 34, 12.)

Q6 → (b). The M extension adds MUL/DIV/REM. A = atomics, F = single-precision float, C = compressed.

Q7 → (c). A normal successful add produces no trap. Syscalls, page faults, and illegal instructions all cause traps/exceptions.

Q8 → (b). The ABI/calling convention standardizes argument registers, caller/callee-saved registers, return values, and stack frame layout so separately compiled code interoperates.

Q9 → (c). $\lceil \log_2 32 \rceil = 5$ bits address 32 registers.

Q10 → (b). User mode is de-privileged: privileged instructions and protected CSRs/resources are inaccessible, enforced by the hardware.

Section B (1 mark each)

Q11.

1 → b (ARM: RISC in mobile/embedded)
2 → c (x86: dominant CISC, variable length)
3 → a (RISC-V: open, modular)
4 → d (I-type: imm[31:20])
5 → e (register file: fast internal storage)

Award 1 mark per correct pair.

Section C (2 marks each: 1 T/F + 1 justification)

Q12. FALSE. Justification: A pure load/store ISA forbids memory operands in arithmetic; you must load both operands into registers, add, then store. Memory-to-memory add is a CISC-style feature.

Q13. TRUE. Justification: RV32I fixes x0 = 0; reads always return 0 and writes are discarded, which simplifies constructing constants and no-ops (e.g. addi x0,x0,0).

Q14. TRUE. Justification: The individual byte values are identical; only their ordering within a multi-byte scalar differs (LSB-first vs MSB-first). Single bytes/strings are unaffected.

Q15. FALSE. Justification: A complex CISC instruction may take many cycles/microcode steps; several simple pipelined RISC instructions can complete the same work faster. "More work per instruction" ≠ "faster."

Q16. TRUE. Justification: Encoding targets as offsets from the PC means the code runs correctly regardless of the absolute load address, enabling position-independent code.

Q17. TRUE. Justification: ecall deliberately raises a synchronous exception, trapping into higher-privilege handler code that services the request and returns to the user program.

Q18. FALSE. Justification: A 32-bit instruction must also hold opcode and register fields, so immediate fields are narrower (e.g. RV32I I-type = 12 bits). Full 32-bit constants need multi-instruction sequences like lui+addi.

[
  {"claim":"5 bits are needed to address 32 registers","code":"from sympy import ceiling, log; result = (ceiling(log(32,2)) == 5)"},
  {"claim":"Little-endian: byte at lowest address of 0x12345678 is 0x78","code":"val=0x12345678; lowest_byte = val & 0xFF; result = (lowest_byte == 0x78)"},
  {"claim":"RV32I I-type immediate is 12 bits, not 32","code":"itype_imm=12; result = (itype_imm < 32 and itype_imm == 12)"},
  {"claim":"Byte order of 0x12345678 little-endian is [0x78,0x56,0x34,0x12]","code":"val=0x12345678; le=[(val>>(8*i))&0xFF for i in range(4)]; result = (le == [0x78,0x56,0x34,0x12])"}
]