Instruction-level semantics and exceptions — Hinglish notes

5.1.12 · Hardware › Instruction Set Architecture (ISA)

WHAT is instruction-level semantics?

Architectural state vs microarchitectural state:

Architectural (visible, ISA se defined)	Microarchitectural (invisible, implementation)
Registers, PC, flags, memory	Pipeline latches, caches, branch predictors, reorder buffer
Sequential model se match karna chahiye	Freely reorder/speculate kar sakta hai

HOW one instruction's semantics is defined

Har instruction ko ek state transition function ke roop mein describe kiya jata hai:

$state_{n + 1} = execute (instr, state_{n})$

Hum yeh first principles se derive karte hain. Ek instruction kya touch kar sakta hai?

Read kuch inputs (registers / memory / immediate / PC).
Compute ek result.
Write kuch outputs (ek register / memory / flags).
Update the PC (next instruction).

Toh, ADD R1, R2, R3 ki poori semantics yeh hai:

Ek branch sirf step 4 ko override karta hai:

WHAT is an exception?

Teen families (vocabulary yaad kar lo — yeh test hoti hai):

Type	Cause	Restartable?	Example
Fault	Correctable problem, commit se pehle detect hua	Haan — wahi instruction dobara execute karo	Page fault, div-by-zero
Trap	Deliberate, instruction ke baad detect hua	Haan — next instruction pe continue karo	System call (`syscall`), breakpoint
Abort	Unrecoverable hardware error	Nahi	Corrupted memory / hardware failure

Interrupt vs Exception (baad mein steel-man):

Exception = synchronous — instruction stream se hi caused hota hai (same input ⇒ same exception).
Interrupt = asynchronous — kisi external device se caused hota hai (timer, keyboard), current instruction se unrelated.

HOW hardware keeps the promise: precise exceptions

Yahi asli baat hai — aur yahan sequential model apna dam dikhata hai.

Pipeline mein yeh kaise achieve hota hai? Instructions out of order ya speculatively compute kar sakti hain, lekin woh strictly program order mein commit (retire, visible) karti hain. Jab exception detect hota hai, hardware:

Offending instruction ko mark karta hai.
Usse aur baad ki saari cheezon ko squash (discard) karta hai — unke results kabhi architectural state tak nahi pahunchte.
Purani saari instructions ko commit karne deta hai.
Exception PC (EPC) aur cause save karta hai, phir vector pe jump karta hai.

Worked examples

Common mistakes (Steel-manned)

Recall Feynman: explain to a 12-year-old

Ek chef ko imagine karo jo recipe follow kar raha hai, ek step at a time. Bahar se dekhne wala sirf har step ke baad finished dish dekhta hai — yeh architectural state hai. Chef secretly do steps ek saath kar sakta hai time bachane ke liye, lekin dekhne wale ko kabhi nahi pata chalna chahiye; dish bilkul aisi dikhni chahiye jaise steps order mein hue hoon. Ab maan lo ek step kehta hai "anday daalo" lekin anday abhi fridge mein hain. Chef ruk jaata hai, koi bhi half-done baad wale steps undo karta hai, aur manager (OS) ko call karta hai: "anday lao!" Yeh ruk-ke-call karna hi exception hai. Anday aane ke baad, chef wahi step dobara karta hai. Agar instead recipe kehti "customer ke liye bell bajao" (ek trap), toh chef kaam finish karke simply next step pe chala jata hai. Trick yeh hai: kitchen ko hamesha ek step boundary pe saaf chhodo taaki koi bhi sambhal sake.

Recall flashcards

#flashcards/hardware

What is instruction-level (architectural) semantics?

Yeh ISA ki guarantee hai ki instructions atomically, ek at a time, program order mein execute hote dikh'te hain, visible architectural state ko transform karte hue.

Architectural vs microarchitectural state?

Architectural = programmer-visible (registers, PC, flags, memory) aur ISA se defined; microarchitectural = implementation detail (pipeline latches, caches, ROB) jo software ko invisible hai.

Give the state-transition form of an instruction.

state_{n+1} = execute(instr, state_n).

Why does default PC update = PC+4?

Fixed-length ISA mein har instruction 4 bytes ka hota hai, isliye next instruction 4 bytes aage hoti hai; PC update karna instruction ki meaning ka part hai.

Define an exception.

Ek unexpected, control-transfer karne wala event jo execution ke dauran detect hota hai aur running program handle nahi kar sakta, control ko ek vector address pe OS handler ke paas bhejta hai.

Fault vs Trap: where does the handler return?

Fault → same (faulting) instruction; Trap → next instruction.

Give an example each of fault, trap, abort.

Fault: page fault / div-by-zero. Trap: syscall / breakpoint. Abort: unrecoverable hardware error.

Exception vs Interrupt?

Exception = synchronous (instruction stream se caused, reproducible); Interrupt = asynchronous (external device, timing-dependent).

Define a precise exception.

Jab handler start ho, saari purani instructions fully commit ho chuki hoon aur faulting instruction plus saari younger instructions ne koi architectural state modify na ki ho.

Why do we need precise exceptions?

Taaki OS ek clean single-instruction boundary inspect kar sake, cause fix kare, aur program cleanly restart kar sake.

How does an out-of-order pipeline stay precise?

Instructions out of order execute karti hain lekin program order mein commit/retire karti hain; fault pe, younger instructions architectural state affect karne se pehle squash ho jaati hain.

If two instructions fault in the same cycle, which is reported?

Sabse purani (earliest in program order), sequential model preserve karte hue.

On a page fault during LW, is the destination register written?

Nahi — precise semantics require karti hai ki faulting instruction architectural state unchanged chhode taaki retry ho sake.

What is the EPC?

Exception PC: handler se return karne ke liye save kiya gaya address (faults ke liye faulting instruction, traps ke liye next instruction).

Connections

Pipelining and Hazards — forwarding/stalls sequential semantics preserve karne ke liye exist karte hain.
Out-of-Order Execution and the Reorder Buffer — in-order commit enforce karne ka mechanism.
Virtual Memory and Page Faults — classic restartable fault.
System Calls and Privilege Levels — OS entry point ke roop mein traps.
Interrupts and I/O — exceptions ka asynchronous cousin.
ISA as a Hardware–Software Contract — architectural state precisely kyun defined hai.