Level 2 — RecallInstruction Set Architecture (ISA)

Instruction Set Architecture (ISA)

⏱ 30 minutes50 marksprintable — key stays hidden on paper

Subject: Hardware Chapter: Instruction Set Architecture (ISA) Difficulty: Level 2 — Recall & short derivations Time limit: 30 minutes Total marks: 50

Q1. State two defining characteristics each of CISC and RISC philosophies, and give one representative commercial ISA for each. (6 marks)

Q2. Define a load/store architecture. Explain briefly why arithmetic instructions in such an architecture cannot operate directly on memory operands. (4 marks)

Q3. The RISC-V RV32I base ISA uses 32-bit fixed-length instructions. An R-type instruction has the fields: funct7 (7) | rs2 (5) | rs1 (5) | funct3 (3) | rd (5) | opcode (7). (a) Verify the total field widths sum to 32 bits. (2 marks) (b) How many distinct general-purpose registers can each of rs1, rs2, rd address, and why? (2 marks) (c) The I-type format replaces funct7 and rs2 with a single immediate field. State the width of that immediate and the range of signed values it can represent. (3 marks)

Q4. Name and briefly describe four distinct addressing modes. For each, give the effective-address computation. (8 marks)

Q5. A 32-bit integer with value 0x12345678 is stored starting at byte address 0x1000. (a) Give the byte stored at each of addresses 0x1000–0x1003 under little-endian ordering. (2 marks) (b) Repeat for big-endian ordering. (2 marks)

Q6. In the RISC-V calling convention (standard ABI): (a) Which register holds the return address after a jal? (1 mark) (b) Name the register category difference between caller-saved and callee-saved registers. (2 marks) (c) Which register conventionally holds the first integer argument and the integer return value? (1 mark)

Q7. List the RISC-V standard extensions denoted by the letters M, A, F, D, C and state in one phrase what functionality each adds. (5 marks)

Q8. Explain the difference between user mode and supervisor/machine mode in a privileged ISA. Give one example of an operation permitted only in the higher-privilege mode. (4 marks)

Q9. Distinguish between a synchronous exception (trap) and an asynchronous interrupt. Give one example of each. (4 marks)

Q10. A RISC-V RV64I core has 32 general-purpose registers, each 64 bits wide. (a) How many bits are needed in an instruction field to select one register? (1 mark) (b) What is the total storage capacity of the register file in bytes? (2 marks)

Answer keyMark scheme & solutions

Q1. (6 marks)

CISC: variable-length instructions; complex multi-cycle instructions; many addressing modes; memory-to-memory operations. (any two, 1 mark each → 2)
RISC: fixed-length instructions; simple single-cycle-ish ops; load/store only; large register file. (any two → 2)
Examples: CISC → x86; RISC → ARM / RISC-V / MIPS. (1 + 1) Why: CISC minimizes instruction count/memory footprint; RISC minimizes hardware complexity to enable pipelining.

Q2. (4 marks)

Load/store architecture: only explicit load and store instructions access memory; all ALU operations use register (or immediate) operands only. (2)
Arithmetic can't touch memory because operands must first be brought into registers — this keeps instructions fixed-length, simplifies decoding, and allows single-cycle ALU execution without embedded memory-access stages. (2)

Q3. (7 marks) (a) $7+5+5+3+5+7 = 32$ ✓ (2) (b) $2^5 = 32$ registers, because each field is 5 bits wide. (2) (c) Immediate width $= 7+5 = 12$ bits. Signed range $= [-2^{11},\, 2^{11}-1] = [-2048,\, +2047]$ . (width 1, range 2)

Q4. (8 marks) — 2 marks each (name + EA formula):

Immediate: operand is in the instruction; EA n/a (value = imm).
Register (direct): operand in register; EA = register content.
Register indirect / base: EA = R[rs1].
Base + displacement: EA = R[rs1] + imm.
PC-relative: EA = PC + imm.
Indexed: EA = R[base] + R[index]. (Any four accepted.)

Q5. (4 marks) Value 0x12345678: MSB=12, then 34, 56, LSB=78. (a) Little-endian (LSB at lowest address): 0x1000=78, 0x1001=56, 0x1002=34, 0x1003=12 (2) (b) Big-endian (MSB at lowest address): 0x1000=12, 0x1001=34, 0x1002=56, 0x1003=78 (2)

Q6. (4 marks) (a) ra (x1). (1) (b) Caller-saved (temporaries, e.g. t0–t6, a0–a7) may be clobbered by a callee, so the caller must save them if needed; callee-saved (s0–s11, sp) must be preserved by the called function. (2) (c) a0 (x10). (1)

Q7. (5 marks) — 1 mark each:

M — integer multiply/divide.
A — atomic memory operations (LR/SC, AMO).
F — single-precision floating point.
D — double-precision floating point.
C — compressed 16-bit instructions.

Q8. (4 marks)

User mode: restricted; runs application code, cannot execute privileged instructions or directly access I/O / control registers. (1.5)
Supervisor/machine mode: full access to system state, control/status registers, memory management, and privileged instructions. (1.5)
Example privileged operation: modifying page tables / accessing CSRs / executing mret / disabling interrupts / I/O port access. (1)

Q9. (4 marks)

Synchronous exception (trap): caused by instruction execution, occurs deterministically at that instruction, e.g. illegal instruction, page fault, ecall, divide-by-zero. (2)
Asynchronous interrupt: caused by an external event unrelated to current instruction, arrives at unpredictable times, e.g. timer interrupt, I/O device interrupt. (2)

Q10. (3 marks) (a) $\log_2 32 = 5$ bits. (1) (b) $32 \times 64 = 2048$ bits $= 2048/8 = 256$ bytes. (2)

[
  {"claim":"R-type field widths sum to 32","code":"result = (7+5+5+3+5+7)==32"},
  {"claim":"5-bit field addresses 32 registers","code":"result = 2**5==32"},
  {"claim":"12-bit signed immediate range is [-2048,2047]","code":"lo=-2**11; hi=2**11-1; result = (lo==-2048) and (hi==2047)"},
  {"claim":"RV64I register file is 256 bytes","code":"result = (32*64)//8==256"},
  {"claim":"register selector needs 5 bits","code":"import sympy; result = sympy.log(32,2)==5"}
]