5.1.12 · D1Instruction Set Architecture (ISA)

Foundations — Instruction-level semantics and exceptions

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Before you can read the parent note, you need a vocabulary. This page builds every word and symbol it uses, starting from nothing. Read top to bottom — each block only uses words already defined above it.


1. The CPU as a little machine that reads a list

Picture a worker with a to-do list. Each line on the list is one order: "add these two things", "go fetch this from storage", "jump to line 40". The worker does line 1, then line 2, then line 3... unless a line says "jump somewhere else".

Figure — Instruction-level semantics and exceptions

That to-do list is a program. Each line is an instruction. This is the whole game: a machine that walks down a list of instructions.


2. State — the stuff the machine remembers

The worker has a few scratch pads and a big storage room. These hold everything the machine "knows" right now.

The machine's state is made of four kinds of things. Meet them one at a time.

2a. Registers

The notation R1, R2, ... just names these boxes. When the parent writes ADD R1, R2, R3, it means "put into box R1 the sum of what's in boxes R2 and R3".

2b. Memory

2c. The Program Counter (PC)

Figure — Instruction-level semantics and exceptions

2d. Flags


3. Two kinds of state: visible vs hidden

Here is the split the whole parent note leans on.

Two more supporting words you'll need for the hidden side:

  • Pipeline — an assembly line where several instructions are worked on at once, each at a different stage. Picture: cars on a factory line, one being painted while the next is welded.
  • Speculation / out-of-order — the machine guessing which way a branch will go, or doing later work early, to save time. Picture: a chef prepping tomorrow's dish while today's is still cooking — but ready to throw it out if the guess was wrong.

You don't need to master these here (see Pipelining and Hazards and Out-of-Order Execution and the Reorder Buffer); you only need to know they're the gears that must stay invisible.


4. Reading the arrows: notation for "what an instruction does"

The parent describes each instruction with arrows and a function. Let's earn every symbol.

The case brace

The branch instruction uses this:


5. Sequential (in-order) execution


6. Exception vocabulary

Now the second half of the topic: what happens when an instruction can't finish.

Figure — Instruction-level semantics and exceptions

Two more distinctions the parent tests:

The three families of exception (fault / trap / abort) are covered fully in the parent — but now you have every word they're built from.


Prerequisite map

Instruction = one to-do line

State snapshot

Registers R1 R2

Memory lockers

Program Counter PC

Flags lights

Architectural state = visible

Pipeline and speculation

Microarchitectural state = hidden

Sequential in-order model

Commit stamps in order

Precise exceptions

Vector and Handler and EPC

Instruction-level semantics and exceptions

Everything on the left feeds the one idea on the right: keep the visible state looking sequential, even through exceptions.


Equipment checklist

Cover the right side and test yourself. If any answer is fuzzy, re-read that section before the parent note.

What is an instruction?
One single order — the smallest unit of work the CPU understands; one line of the to-do list.
What is state?
A complete snapshot of every value the machine currently holds.
Name the four pieces of architectural state.
Registers, memory, the PC, and status flags.
What does the PC hold?
The address of the next instruction to run — the finger on the to-do list.
Why does the PC often increase by 4?
Each instruction is 4 bytes long, so the next one sits 4 addresses further on.
What does mean?
Put the value into place (copy right into left).
Read in plain words.
Running one instruction turns the old snapshot into the new snapshot.
Architectural vs microarchitectural state?
Architectural = visible parts the ISA promises (registers, PC, flags, memory); microarchitectural = hidden gears (pipeline, caches, predictors) you may not rely on.
What does commit / retire mean?
The moment an instruction's result is stamped into visible architectural state.
Sequential execution — the mental picture?
Dominoes falling one by one; the next never tips until the current has fully landed.
What is an exception?
A forced jump away from normal flow because an instruction hit a problem mid-execution.
Handler vs vector vs EPC?
Handler = the OS rescue routine; vector = the fixed address it lives at; EPC = the saved PC bookmark of where to return.
Synchronous vs asynchronous?
Synchronous (exception) is caused by the instruction itself and repeats; asynchronous (interrupt) is external timing and doesn't.
Define a precise exception in one line.
The visible state looks exactly like a clean stop right before the bad instruction — nothing after it touched.

Ready? Now the parent note topic reads like plain English. For where these ideas lead next, see ISA as a Hardware–Software Contract, Virtual Memory and Page Faults, and System Calls and Privilege Levels.