Noesis
6.4.9Power, Thermal & Reliability

Voltage droop and decoupling capacitors

1,885 words9 min readdifficulty · medium
🇮🇳 Yeh note Hinglish mein padho →

WHAT is voltage droop?

The PDN is not just a resistor. It has three parts that matter on three timescales:

Element Symbol Dominates on timescale
Resistance RR steady state (DC)
Inductance LL fast current changes (di/dtdi/dt)
Capacitance CC provides charge locally

HOW a decoupling capacitor fixes it (derive from scratch)

Step 1 — What a capacitor stores. Charge Q=CVQ = CV. Differentiate: iC=dQdt=CdVdti_C = \frac{dQ}{dt} = C\frac{dV}{dt}

Step 2 — Ask how much the voltage drops while the cap alone supplies the load. Rearrange for the voltage change while delivering current ΔI\Delta I for a duration Δt\Delta t: ΔV=1C∫i dt≈ΔI⋅ΔtC\Delta V = \frac{1}{C}\int i\,dt \approx \frac{\Delta I \cdot \Delta t}{C} Why this step? We integrated iC=C dV/dti_C = C\,dV/dt over the current spike. Bigger CC ⇒ smaller droop. This is the whole reason capacitors are big.

Step 3 — Size the capacitor. Set an allowed droop budget ΔVmax\Delta V_{max}: C≥ΔI⋅ΔtΔVmax\boxed{C \ge \frac{\Delta I \cdot \Delta t}{\Delta V_{max}}}

Step 4 — Why one capacitor is not enough (the frequency picture). Every real cap has parasitic series inductance (ESLESL) and resistance (ESRESR): Zcap(ω)=ESR+jωESL+1jωCZ_{cap}(\omega) = ESR + j\omega ESL + \frac{1}{j\omega C}

  • At low ω\omega: 1ωC\frac{1}{\omega C} dominates → capacitor "works."
  • At its self-resonant frequency f0=12πESL⋅Cf_0 = \dfrac{1}{2\pi\sqrt{ESL\cdot C}}: impedance is minimum =ESR=ESR.
  • Above f0f_0: ωESL\omega ESL dominates → the cap looks like an inductor and stops helping.

Why this matters: no single cap covers all frequencies, so we use a hierarchy.

Figure — Voltage droop and decoupling capacitors

Worked examples

Common mistakes (steel-manned)

Recall Feynman: explain to a 12-year-old

Imagine a water tap far away and a kid who suddenly gets very thirsty. If the kid gulps fast, water can't rush down the long pipe instantly — the pressure at the cup drops. So we keep a cup of water right next to the kid (the capacitor). When he gulps, the cup empties first and keeps the pressure up until the far tap catches up. Small cups react instantly but run dry; big tanks are slow but hold a lot — so we keep several sizes at different distances.

Flashcards

What causes voltage droop physically?
PDN impedance (RR, LL, CC) reacting to a fast change in load current: ΔV=−ΔI⋅ZPDN\Delta V = -\Delta I \cdot Z_{PDN}.
Formula for inductive droop?
VL=L di/dtV_L = L\,di/dt — depends on rate of current change, not magnitude.
Formula to size a decoupling cap for a current step?
C≥ΔI⋅Δt/ΔVmaxC \ge \Delta I \cdot \Delta t / \Delta V_{max}.
Why is di/dtdi/dt more dangerous than large steady current?
Inductors resist current change, so fast slews create big L di/dtL\,di/dt voltage spikes even at modest current.
What is a capacitor's self-resonant frequency?
f0=1/(2πESL⋅C)f_0 = 1/(2\pi\sqrt{ESL\cdot C}); below it it's capacitive, above it it's inductive (useless).
Why use a hierarchy of decoupling caps?
Each cap size covers a different frequency band; no single cap has low impedance across all frequencies.
Why place decoupling caps close to the die?
To minimize loop inductance between cap and load so charge can be delivered fast.
What happens if droop pushes V below VminV_{min}?
Transistors fail timing → wrong bits / logic errors.
Which cap type handles the fastest (ns) spikes?
On-die / on-package caps (smallest, closest, lowest inductance).
At resonance, what is a capacitor's impedance?
Its minimum, equal to the ESRESR.

Connections

Concept Map

drives

multiplies dI

villain via V=L di/dt

if severe

causes

supplies

counteracts

derives

limited by

requires

flattens

Fast current change dI/dt

PDN impedance Z_PDN

Wire inductance L

Voltage droop delta V

V below V_min

Wrong bits timing failure

Decoupling capacitor

Local stored charge Q=CV

Sizing C >= dI dt / dVmax

Parasitic ESL and ESR

Multiple caps across frequencies

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, jab CPU ka core achanak se bahut saare transistors ek saath switch karta hai, to usko instantly bahut current chahiye hota hai. Problem ye hai ki power supply door hai aur beech ke wires me inductance hoti hai. Inductor current ke change ko rokta hai — yani VL=L di/dtV_L = L\,di/dt. Isliye chip ke power pins par voltage thoda gir jaata hai, isko voltage droop kehte hain. Agar ye droop VminV_{min} se niche chala gaya to chip galat bits produce karega. Yaad rakho: khatra current kitna bada hai usse nahi, balki kitni tezi se badla usse hota hai.

Iska solution hai decoupling capacitor — ek chhota charge ka "bucket" jo chip ke bilkul paas rakha jaata hai. Jab current spike aata hai, ye capacitor apna stored charge turant de deta hai aur voltage ko upar hold karta hai, jab tak door wali supply catch up na kar le. Formula simple hai: C≥ΔI⋅Δt/ΔVmaxC \ge \Delta I \cdot \Delta t / \Delta V_{max}. Jitna bada droop budget chhota chahiye, utna bada cap.

Lekin ek hi bada capacitor kaafi nahi. Har cap me thodi si parasitic inductance (ESLESL) hoti hai, isliye ek self-resonant frequency f0f_0 ke upar wo cap inductor ki tarah behave karne lagta hai aur bekaar ho jaata hai. Isliye hum hierarchy use karte hain: bade bulk caps (slow, kHz-MHz), MLCC (MHz), aur on-die caps (sabse fast, ns-level). Rule yaad rakho — fast events ke liye charge physically paas hona chahiye, kyunki door rakhne se loop inductance badh jaati hai. Bas yahi decoupling ka pura funda hai.

Go deeper — visual, from zero

D1FoundationsEvery symbol from zero · 2,433 wordsD2Visual walkthroughThe derivation in pictures · 2,867 wordsD3Worked examplesEvery scenario covered · 4,014 wordsD4ExercisesGraded, full solutions · 3,405 wordsD5Question bankConcept traps, quick reveals · 2,492 words

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