Voltage droop and decoupling capacitors: Worked examples

This deep-dive drills the parent topic Voltage droop and decoupling capacitors into every case that can appear on an exam or a real board. We build each answer from the two laws you already met, but here we hunt down the degenerate, limiting, and sign cases the parent glossed over.

Before any numbers, let me earn every symbol we lean on, in plain words:

Definition Every symbol on this page, earned before use

$Δ I$ — how much the current jumps, in amps (A). A positive $Δ I$ means the chip suddenly wants more current.
$Δ t$ — how long that jump takes, in seconds (s). Smaller $Δ t$ = faster = nastier.
$\frac{d i}{d t}$ — the slope of the current-versus-time line: amps per second (A/s). Read it off a graph as "rise over run".
$Δ V$ — the resulting wobble of the voltage rail, in volts (V). A droop is a negative $Δ V$ (the rail sags).
$V_{L}$ — the voltage that appears across an inductor when its current is changing, in volts (V). This is the "villain" voltage that steals from the rail during a fast edge.
$Q$ — electric charge, the amount of "electricity" a capacitor stores, in coulombs (C). One coulomb is one amp flowing for one second, so $Q = I \cdot t$ .
$L$ — inductance of the wire/path, in henries (H): how strongly the path fights a change in current. Picture the heaviness of water in a long pipe that hates to speed up or slow down.
$C$ — capacitance of the decoupling cap, in farads (F): how big the "cup of charge" is. Bigger $C$ = deeper cup = smaller sag for the same charge drawn.
$R$ — resistance, in ohms ( $Ω$ ): the steady voltage-per-amp toll a wire always charges, even at DC.
$E S R$ — Equivalent Series Resistance: the small unavoidable resistance inside a real capacitor (in $Ω$ ).
$E S L$ — Equivalent Series Inductance: the small unavoidable inductance inside a real capacitor (in H), from its own leads/plates.
$j$ — the imaginary unit ( $j = - 1$ ; engineers write $j$ instead of $i$ so it isn't confused with current). It is a bookkeeping symbol that tracks a $9 0^{\circ}$ phase shift in AC circuits — you never need to "compute" it, only carry it.

The scenario matrix

Every problem on this topic is one cell of this table. "Case class" = the physical situation you are handed; "What is being tested" = the single formula or idea that cracks it. Read each row as "if the situation is X, reach for tool Y."

#	Case class (the situation handed to you)	What is being tested (the tool that cracks it)	Example
A	You are given a fast current step and a droop budget, asked for cap size	Sizing formula $C \geq Δ I Δ t /Δ V_{ma x}$	Ex 1
B	Current is rising through inductance ( $d i / d t > 0$ )	$V_{L} = L d i / d t$ gives a positive number → a sag	Ex 2
C	Current is falling through inductance ( $d i / d t < 0$ )	Same law; negative slope → negative $V_{L}$ → an overshoot	Ex 3
D	Current is constant (steady DC, $d i / d t = 0$ )	Inductor vanishes ( $V_{L} = 0$ ); only Ohm's $I R$ drop remains — that is why this cell is "IR-only"	Ex 4
E	The transition time is squeezed toward zero ( $Δ t \to 0$ )	Limiting behaviour: droop $\to \infty$ , so caps must be local	Ex 5
F	You are asked at what frequency a real cap stops helping	Self-resonance $f_{0}$ ; capacitive band vs inductive band	Ex 6
G	A word problem: DVFS wakes several cores at once	Translate the words into $Δ I$ and $Δ t$ , then apply A & B	Ex 7
H	Exam twist: a real cap that both drains AND has its own $E S L$	Superpose two droops — charge term + $E S L d i / d t$ term	Ex 8
I	Reverse/design: droop and cap given, find the fastest step it covers	Invert the sizing box to solve for $Δ t$	Ex 9

We cover positive and negative $d i / d t$ (cells B & C), the zero case (D), the limit (E), a frequency-domain case (F), and word/exam/reverse problems (G–I). No cell is left empty.

Cell A — Size a decoupling capacitor

Worked example Ex 1 (Cell A) — sizing from a current step

A core draws a step of $Δ I = 30 A$ that lasts $Δ t = 3 ns$ . The droop budget is $Δ V_{ma x} = 60 mV$ . Find the minimum capacitance.

Forecast: guess the order of magnitude — nanofarads? microfarads? millifarads?

Find the charge $Q$ the cap must deliver. Recall $Q$ (charge, coulombs) $= I \cdot t$ , so $Q = Δ I Δ t = 30 \times 3 \times 1 0^{- 9} = 9 \times 1 0^{- 8} C = 90 nC$ . Why this step? A capacitor's only job here is to hand over charge; charge is current × time.
Divide by the allowed sag. $C \geq \frac{Q}{Δ V _{ma x}} = \frac{9 \times 1 0 ^{- 8}}{0.06} = 1.5 \times 1 0^{- 6} F = 1.5 μ F$ . Why this step? $Q = C Δ V$ , so for a fixed charge, a bigger $C$ means a smaller voltage drop. Solve for $C$ at the worst allowed drop.

Verify: plug back — $C Δ V_{ma x} = 1.5 \times 1 0^{- 6} \times 0.06 = 9 \times 1 0^{- 8} C$ = the 90 nC we needed. ✓ Units: $\frac{A \cdot s}{V} = \frac{C}{V} = F$ . ✓ Microfarads, as forecast for a MLCC.

Sign convention for the capacitor droop law

Cells B & C — the SIGN of $d i / d t$ decides sag vs overshoot

This is the part the parent note assumed but never drew. The direction the current changes flips the sign of the voltage bump. Figure 1 below plots two panels stacked: the top panel is current versus time (blue-shaded rising edge, pink-shaded falling edge), and the bottom panel is the resulting rail voltage. Trace the shaded bands downward: the rising edge (top, blue) lines up with a sag (bottom, blue arrow "DROOP"); the falling edge (top, pink) lines up with a spike (bottom, pink arrow "OVERSHOOT").

Figure — Voltage droop and decoupling capacitors

Figure 1 — Top: load current with a rising edge (blue band) and a falling edge (pink band). Bottom: the rail voltage around its 1.0 V nominal (yellow dashed). Rising current → droop; falling current → overshoot. Same edge magnitude, opposite rail direction.

Worked example Ex 3 (Cell C) — falling current, overshoot

Same $L = 150 pH$ . Now the core finishes its work: current drops from $60 A$ back to $10 A$ in $1 ns$ . Find the rail wobble and its sign.

Forecast: same size number as Ex 2, but which way does the rail move?

Slope, with sign. $\frac{d i}{d t} = \frac{10 - 60}{1 \times 1 0 ^{- 9}} = - 5 \times 1 0^{10} A/s$ . Negative — current is falling. Why this step? Keep the sign honest; it is the whole point of this cell.
Apply the law. $V_{L} = 150 \times 1 0^{- 12} \times (- 5 \times 1 0^{10}) = - 7.5 V$ . Why this step? Same law, negative slope → negative $V_{L}$ , which appears at the chip as the rail springing up by $7.5 V$ (an overshoot).

Verify: magnitude identical to Ex 2 ( $7.5 V$ ), sign opposite. ✓ Matches the pink falling edge in Figure 1. Lesson: the end of a current burst is as dangerous as the start — decoupling caps also absorb overshoot.

Cell D — the zero/degenerate case ( $d i / d t = 0$ )

Worked example Ex 4 (Cell D) — steady DC, no change

A block draws a constant $I = 40 A$ through a path with $L = 150 pH$ and $R = 0.5 m Ω$ . What is the droop right now (in steady state)?

Forecast: does the inductance matter if nothing is changing?

Inductive term. Current is constant, so $\frac{d i}{d t} = 0$ , giving $V_{L} = L \cdot 0 = 0 V$ . Why this step? An inductor only reacts to change. A steady river through it develops no voltage. This is the degenerate case where the "villain" disappears — which is why this cell reduces to IR-only.
Resistive term survives. $V_{R} = I R = 40 \times 0.5 \times 1 0^{- 3} = 0.02 V = 20 mV$ . Why this step? Resistance always drops voltage in proportion to current — it never sleeps, even at DC.

Verify: total steady droop $= V_{L} + V_{R} = 0 + 20 mV = 20 mV$ . ✓ Only the resistor contributes; this is the "DC droop" the parent's table attributes to $R$ . A cap does not fix DC droop — that's the regulator's job.

Cell E — the limit ( $Δ t \to 0$ )

Worked example Ex 5 (Cell E) — squeeze the transition to zero

Take Ex 2's step ( $Δ I = 50 A$ , $L = 150 pH$ ) but ask: what happens to $V_{L}$ as the transition time $Δ t$ shrinks: $1 ns$ , $100 ps$ , $10 ps$ ?

Forecast: does the droop level off, or keep growing without bound?

Write droop as a function of $Δ t$ . $V_{L} (Δ t) = L \frac{Δ I}{Δ t} = 150 \times 1 0^{- 12} \times \frac{50}{Δ t}$ . Why this step? Fix everything except $Δ t$ so we can watch the trend.
Evaluate the three points.
- $Δ t = 1 ns$ : $V_{L} = 7.5 V$ .
- $Δ t = 100 ps$ : $V_{L} = 75 V$ .
- $Δ t = 10 ps$ : $V_{L} = 750 V$ . Why this step? Numbers make the trend undeniable.
Take the limit. As $Δ t \to 0$ , $V_{L} = \frac{L Δ I}{Δ t} \to \infty$ . Why this step? Dividing a fixed number by something heading to zero blows up. This is the mathematical statement of "you can never make current jump instantly through an inductor."

Verify: each tenfold decrease in $Δ t$ multiplies $V_{L}$ by ten (7.5 → 75 → 750). ✓ The limit is the reason charge must come from a nearby, low-inductance cap: no matter how fast the edge, the local cap's $Δ V = Δ I Δ t / C$ actually shrinks as $Δ t \to 0$ , so the cap wins exactly where the wire fails.

Cell F — self-resonance and the three frequency bands

Now we switch from time to frequency. Why frequency? Because a real cap is not a pure capacitor — it has series inductance ( $E S L$ , its own internal inductance) and resistance ( $E S R$ , its own internal resistance), and whether the cap helps depends on how fast (what frequency) the disturbance is. Figure 2 below plots the cap's impedance magnitude $∣ Z ∣$ (vertical axis, ohms) against frequency $f$ (horizontal axis, Hz), both on log scales. The blue dashed line is the falling capacitive reactance $1/ (ω C)$ ; the pink dashed line is the rising inductive reactance $ω E S L$ ; the solid white curve is the real cap, which follows blue on the left, dips to the yellow $E S R$ floor, then follows pink on the right.

Figure 2 — Impedance of a real capacitor vs frequency. Left of $f_{0}$ : capacitive (blue), the cap works. At $f_{0}$ (yellow line): impedance bottoms out at $E S R$ (yellow dotted floor). Right of $f_{0}$ : inductive (pink), the cap is useless. $ω = 2 π f$ is angular frequency.

Worked example Ex 6 (Cell F) — find

$f_{0}$ and check both sides A cap has $C = 220 nF$ and $E S L = 0.8 nH$ , $E S R = 5 m Ω$ . Find its self-resonant frequency, and its impedance at $f_{0}$ .

Forecast: tens of MHz? hundreds?

Compute the product. $E S L \cdot C = 0.8 \times 1 0^{- 9} \times 220 \times 1 0^{- 9} = 1.76 \times 1 0^{- 16} s^{2}$ . Why this step? $f_{0}$ needs the square root of $E S L \cdot C$ ; get the product first.
Take the resonance formula (derived above). $f_{0} = \frac{1}{2 π 1.76 \times 1 0 ^{- 16}} = \frac{1}{2 π \times 1.327 \times 1 0 ^{- 8}} \approx 1.20 \times 1 0^{7} Hz = 12.0 MHz$ . Why this step? This is the frequency where inductive and capacitive reactances are equal and cancel.
Impedance at $f_{0}$ . At exactly $f_{0}$ the reactances cancel, leaving $∣ Z ∣ = E S R = 5 m Ω$ . Why this step? Minimum impedance = the resistive floor (the yellow dotted line in Figure 2). Below $f_{0}$ the cap helps; above it, add a smaller cap with higher $f_{0}$ .

Verify: $1.76 \times 1 0^{- 16} = 1.327 \times 1 0^{- 8}$ ; $2 π \times 1.327 \times 1 0^{- 8} = 8.34 \times 1 0^{- 8}$ ; reciprocal $= 1.199 \times 1 0^{7} Hz$ . ✓ ≈ 12 MHz. See LC resonance and impedance for the general $L C$ picture and Parasitic inductance and ESL/ESR for where $E S L$ comes from.

Cell G — a real-world word problem (DVFS)

Worked example Ex 7 (Cell G) — cores wake up under DVFS

A power-management unit uses Dynamic voltage and frequency scaling (DVFS) to wake 8 idle cores at once. Each core adds $6 A$ when it turns on, and the gating hardware ramps them all up together in $Δ t = 4 ns$ . The rail is $0.9 V$ and $V_{min} = 0.82 V$ . Path inductance to the nearest bulk cap is $L = 120 pH$ . Is the die safe on inductive droop alone, and if not, what cap prevents it?

Forecast: will 8 cores at once trip $V_{min}$ ?

Translate words to $Δ I$ . $Δ I = 8 \times 6 = 48 A$ . Why this step? "8 cores × 6 A" is simply the total simultaneous demand — this is di-dt and simultaneous switching noise in action.
Inductive droop. $V_{L} = L \frac{Δ I}{Δ t} = 120 \times 1 0^{- 12} \times \frac{48}{4 \times 1 0 ^{- 9}} = 120 \times 1 0^{- 12} \times 1.2 \times 1 0^{10} = 1.44 V$ . Why this step? The rate of change through the path inductance sets the raw droop before any local cap acts.
Compare to budget. Allowed droop $= 0.9 - 0.82 = 0.08 V = 80 mV$ . Since $1.44 V ≫ 80 mV$ , not safe — the far cap is behind too much inductance. Why this step? A go/no-go check against $V_{min}$ .
Size the local cap that holds the rail. $C \geq \frac{Δ I Δ t}{Δ V _{ma x}} = \frac{48 \times 4 \times 1 0 ^{- 9}}{0.08} = \frac{1.92 \times 1 0 ^{- 7}}{0.08} = 2.4 \times 1 0^{- 6} F = 2.4 μ F$ . Why this step? A local, low- $E S L$ cap supplies the $Q = Δ I Δ t = 192 nC$ so the wire's $L d i / d t$ never appears at the die.

Verify: charge $= 48 \times 4 \times 1 0^{- 9} = 1.92 \times 1 0^{- 7} C$ ; $C Δ V = 2.4 \times 1 0^{- 6} \times 0.08 = 1.92 \times 1 0^{- 7} C$ . ✓ Match. The $2.4 μ F$ local cap, not a bigger far one, is the fix.

Cell H — exam twist: superpose both effects

Worked example Ex 8 (Cell H) — cap holds up, but its own ESL bites

A $1 μ F$ cap ( $E S L = 0.5 nH$ , $E S R = 8 m Ω$ ) supplies a $Δ I = 20 A$ step in $Δ t = 2 ns$ . Estimate the total droop, combining (a) the charge-depletion droop and (b) the extra droop across the cap's own $E S L$ .

Forecast: which term dominates — the $C$ term or the $E S L$ term?

Charge-depletion droop (the $C$ term). Magnitude $Δ V_{C} = \frac{Δ I Δ t}{C} = \frac{20 \times 2 \times 1 0 ^{- 9}}{1 0 ^{- 6}} = 4 \times 1 0^{- 2} V = 40 mV$ . Why this step? The bucket empties by this much as it delivers charge (a sag, per the signed law above).
ESL droop (the inductive term inside the cap). $Δ V_{E S L} = E S L \frac{Δ I}{Δ t} = 0.5 \times 1 0^{- 9} \times \frac{20}{2 \times 1 0 ^{- 9}} = 0.5 \times 1 0^{- 9} \times 1 0^{10} = 5 V$ . Why this step? Even the cap's own tiny series inductance obeys $L d i / d t$ during the fast edge.
Compare and combine. $Δ V_{E S L} = 5 V ≫ Δ V_{C} = 40 mV$ . Total worst-case magnitude $\approx 5.04 V$ , utterly dominated by $E S L$ . Why this step? The twist: even a "good" cap fails on a 2 ns edge because of its own $E S L$ — this is exactly why we need still-smaller, lower- $E S L$ on-package caps for the fastest events.

Verify: $Δ V_{C} = 40 mV$ ✓; $Δ V_{E S L} = 5 V$ ✓. The $E S L$ term is $125 \times$ larger. ✓ Lesson: for ns-scale spikes, $E S L$ — not $C$ — decides everything (see Parasitic inductance and ESL/ESR).

Cell I — reverse/design problem

Worked example Ex 9 (Cell I) — given the cap, how fast a step can it survive?

You already have a $0.47 μ F$ cap installed. The droop budget is $Δ V_{ma x} = 50 mV$ and the expected current step is $Δ I = 15 A$ . What is the longest transition $Δ t$ this cap can cover on charge alone?

Forecast: nanoseconds? tens of nanoseconds?

Invert the sizing formula. From $C \geq \frac{Δ I Δ t}{Δ V _{ma x}}$ , solve for the boundary $Δ t$ : $Δ t = \frac{C Δ V _{ma x}}{Δ I}$ . Why this step? The design question flips which variable is unknown; algebra, no new physics.
Plug in. $Δ t = \frac{0.47 \times 1 0 ^{- 6} \times 0.05}{15} = \frac{2.35 \times 1 0 ^{- 8}}{15} = 1.567 \times 1 0^{- 9} s \approx 1.57 ns$ . Why this step? Direct substitution of the known cap, budget, and step.

Verify: plug back — $\frac{Δ I Δ t}{C} = \frac{15 \times 1.567 \times 1 0 ^{- 9}}{0.47 \times 1 0 ^{- 6}} = \frac{2.35 \times 1 0 ^{- 8}}{4.7 \times 1 0 ^{- 7}} = 0.05 V = 50 mV$ . ✓ Exactly the budget. If the real event is faster than 1.57 ns you must add a faster (smaller, lower- $E S L$ ) cap upstream.

Recall Which cell am I in? (decide before computing)

Given a current step and a droop budget, find $C$ ? ::: Cell A — use $C \geq Δ I Δ t /Δ V_{ma x}$ .
Current is rising through inductance? ::: Cell B — $V_{L} > 0$ , a droop (sag).
Current is falling? ::: Cell C — $V_{L} < 0$ , an overshoot (spike up).
Current is constant? ::: Cell D — $V_{L} = 0$ , only $I R$ remains.
Transition time $\to 0$ ? ::: Cell E — droop $\to \infty$ ; only a local cap escapes it.
Asked at what frequency the cap stops helping? ::: Cell F — above $f_{0} = 1/ (2 π E S L C)$ .

Connections

6.4.09 Voltage droop and decoupling capacitors (Hinglish)
Power Delivery Network (PDN)
Parasitic inductance and ESL/ESR
di-dt and simultaneous switching noise
Clock timing margin and Vmin
Dynamic voltage and frequency scaling (DVFS)
LC resonance and impedance

Worked examples — Voltage droop and decoupling capacitors