Visual walkthrough — Voltage droop and decoupling capacitors

Nothing here is assumed. If you have never seen $\frac{dV}{dt}$, an "impedance", or a "resonance", you will meet each one on its own diagram in the order you need it.

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Step 1 — What is actually being asked for: charge, delivered on time

WHAT. A chip is a huge crowd of tiny switches. When a lot of them flip at the same instant, the chip suddenly needs a burst of electric current. Current just means "charge flowing per second". So the real request is: deliver a bucket of charge in a very short time.

WHY start here. Before any formula, we must be clear what "droop" is a failure of. It is a failure to deliver charge fast enough. Everything downstream is bookkeeping on that one sentence.

PICTURE. Look at the figure. On the left is a far-away power supply. On the right is the chip (the load). Between them runs a wire — drawn long on purpose. The amber burst at the chip is the sudden demand.

The symbol $\frac{dQ}{dt}$ is not scary: it is the slope of the charge-versus-time graph — steep slope means charge is moving fast, i.e. big current.

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Step 2 — Why the wire fights us: inductance and $L\frac{di}{dt}$

WHAT. The long wire from supply to chip is not a free connection. Every wire has inductance, written $L$, measured in henries. Inductance is a wire's reluctance to change its current — like the heaviness of water already moving in a pipe.

WHY this tool, and why now. We need to explain why a supply that is "big enough" on average still can't respond instantly. Resistance ($V=IR$) can't explain it: resistance cares about how much current, not how suddenly. The quantity that punishes suddenness is inductance, through the law $V_L=L\frac{di}{dt}$. So we reach for $L$ precisely because the problem is about a fast change, and $\frac{di}{dt}$ is the mathematical name for "how fast the current is changing".

PICTURE. The current step is drawn as a ramp rising from $0$ to $\Delta I$ over a tiny time $\Delta t$. The steeper that ramp, the larger the voltage the inductor throws back.

$$V_L=\underset{\begin{array}{c}\text{wire’s}\\ \text{inductance}\end{array}}{\underbrace{L}}\cdot \underset{\begin{array}{c}\text{slope of the}\\ \text{current ramp}\end{array}}{\underbrace{\frac{di}{dt}}}$$

• $L$ — a fixed property of the wire's geometry. Longer / thinner loop ⇒ bigger $L$.
• $\frac{di}{dt}$ — how steep the amber ramp is. Same $\Delta I$ but half the time ⇒ double the droop.

This is the $di/dt$ problem, and $L$ here is the parasitic inductance of the delivery path.

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Step 3 — The rescue: keep a bucket of charge next to the chip

WHAT. If the far wire cannot ramp its current fast enough, we place a local reservoir of charge millimetres from the chip: a capacitor, $C$. In the first nanoseconds the capacitor empties itself into the chip, and the slow wire is off the hook until it catches up.

WHY. We are physically bypassing the villain of Step 2. Charge that is already sitting next to the load does not have to travel down the long inductive wire, so its $L$ barely matters. Speed comes from proximity, not from a fatter supply.

PICTURE. Same layout as Step 1, but now a capacitor sits right beside the chip on a tiny low-inductance loop. The amber arrows show charge flowing out of the cap (fast, short path) while the wire's current is still lazily ramping up.

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Step 4 — Turn "$Q=CV$" into a droop equation

WHAT. We want a number for how far the voltage sags while the capacitor alone feeds the chip. Start from $Q=CV$ and ask how $V$ moves as charge leaves.

WHY differentiate. $Q=CV$ is a static statement. The chip's demand is a changing thing. To connect a changing charge to a changing voltage we differentiate — differentiation is exactly the tool that turns "total stored" into "rate of change".

$$i_C=\frac{dQ}{dt}=C\frac{dV}{dt}$$

• $i_C$ — here written in the passive-sign convention: $i_C$ is the current flowing into the capacitor's $+$ terminal, and $\frac{dV}{dt}$ is measured with the same $+/-$ reference. When the cap charges up, $\frac{dV}{dt}>0$ and $i_C>0$.
• $\frac{dV}{dt}$ — how fast the cap's voltage changes.

PICTURE. The cap's voltage starts at the rail and slides down a short slope as it delivers current; the area of the current pulse is the charge that left it.

Now add up (integrate) the charge that leaves over the whole spike. Integration just means "add up all the little bits of charge $idt$". Writing $\Delta V$ for the magnitude of the voltage drop and $i(t)$ for the magnitude of the current the cap sources:

$$\Delta V=\frac{1}{C}\int idt\underset{\begin{array}{c}\text{rectangular}\\ \text{pulse}\end{array}}{\approx }\frac{\stackrel{\text{total charge }Q\text{ delivered}}{\overbrace{\Delta I\cdot \Delta t}}}{C}$$

• The $\approx$ assumes a constant-current (rectangular) pulse: current $\Delta I$ held flat for a duration $\Delta t$, so $\int idt=\Delta I\cdot \Delta t$ exactly. A real spike has a shape, but this rectangle is the standard worst-case bookkeeping — it over-estimates the charge for a spike that ramps, giving a safe cap size.
• $\Delta I\cdot \Delta t$ — the size of the chip's current pulse times how long it lasts = the coulombs the cap had to hand over.
• Divide by $C$ (coulombs per volt) ⇒ the volts lost. Bigger $C$ ⇒ smaller droop. This single line is the entire reason capacitors are the fix.

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Step 5 — Size the capacitor (the first boxed result)

WHAT. We are allowed a droop budget: the voltage may sag by at most $\Delta V_{max}$ before it hits $V_{min}$ and the chip makes wrong bits. Impose $\Delta V\le \Delta V_{max}$ in the Step-4 formula and solve for $C$.

WHY solve for $C$. Step 4 gave droop as an output once $C$ is known — but the engineer's real question is the reverse: "given a droop I refuse to exceed, what is the smallest cap that guarantees it?" So we treat $\Delta V_{max}$ as a fixed limit, substitute it in place of $\Delta V$, and rearrange the inequality to put $C$ alone on one side. Algebraically isolating $C$ turns a description of droop into a design rule — a threshold the chosen cap must clear. The inequality direction ($\ge$) survives because $C$ sits in the denominator, so a larger $C$ can only make droop smaller — safely below budget.

$$\Delta V=\frac{\Delta I\Delta t}{C}\le \Delta V_{max}⟹\boxed{C\ge \frac{\Delta I\cdot \Delta t}{\Delta V_{max}}}$$

• Numerator = charge you must supply.
• Denominator = volts you're willing to lose supplying it.

PICTURE. Two droop curves for the same spike: a small cap dips below the red $V_{min}$ line (failure); a correctly sized cap stays above it.

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Step 6 — The catch: a real capacitor is also an inductor

WHAT. No physical capacitor is pure. Its leads and plates add a small series inductance $ESL$ and resistance $ESR$. So the capacitor's opposition to current — its impedance $Z$ — is a sum of three parts.

WHY introduce impedance. Steps 4–5 assumed the cap is always ready. But a cap's $ESL$ means that at high enough frequency it, too, suffers the $Ldi/dt$ villain internally. To see which frequencies it still helps at, we need a quantity that measures opposition-versus-frequency: that is impedance $Z(\omega )$, where $\omega =2\pi f$ is the angular frequency (how many radians of a wiggle pass per second).

$$Z_{cap}(\omega )=\underset{\text{flat floor}}{\underbrace{ESR}}+\underset{\begin{array}{c}+\text{imaginary,}\\ \text{grows with }f\end{array}}{\underbrace{j\omega ESL}}\underset{\begin{array}{c}-\text{imaginary,}\\ \text{shrinks with }f\end{array}}{\underbrace{-\frac{j}{\omega C}}}$$

• The capacitive term is written as it appears, $\frac{1}{j\omega C}$, but note $\frac{1}{j}=-j$, so $\frac{1}{j\omega C}=-\frac{j}{\omega C}$. It is a negative-imaginary (capacitive) reactance.
• $j\omega ESL$ is positive-imaginary (inductive) reactance. The two imaginary parts have opposite sign, so they cancel at one frequency — that cancellation is the whole point of the next step.
• $j$ is just a bookkeeping tag meaning "this part pushes 90° out of step"; the opposite signs are why inductive and capacitive effects subtract rather than add.
• $ESR$ — a fixed real resistive floor.
• $\frac{1}{\omega C}$ — the magnitude of the capacitive part; huge at low $f$, tiny at high $f$.
• $\omega ESL$ — the magnitude of the inductive part; tiny at low $f$, huge at high $f$.

PICTURE. The classic V-shaped impedance curve on log axes: the capacitive slope falling, the inductive slope rising, meeting at a bottom where they cancel.

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Step 7 — The bottom of the V: self-resonant frequency

WHAT. The two competing terms are equal in magnitude at one special frequency — the self-resonant frequency $f_0$. Below it the cap is capacitive (good). Above it, $ESL$ wins and the "capacitor" behaves like an inductor — useless for decoupling.

WHY. Setting the two reactance magnitudes equal, $\frac{1}{\omega C}=\omega ESL$ (the crossover where the opposite-sign imaginary parts cancel), and solving gives the frequency where impedance bottoms out at just $ESR$. This is LC resonance.

$$\frac{1}{{\omega }_{0}C}={\omega }_{0}ESL⟹\boxed{f_0=\frac{1}{2\pi \sqrt{ESL\cdot C}}}$$

• Bigger $C$ or bigger $ESL$ ⇒ lower $f_0$ ⇒ the cap goes "inductive" earlier.

PICTURE. Same V-curve, now with $f_0$ marked at the minimum and the floor labelled $ESR$; a shaded amber band shows the useful (capacitive) region to its left.

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Step 8 — Edge & degenerate cases (never leave a scenario unshown)

WHY cover the limits. A formula only feels trustworthy once you've watched it behave at the extremes. Each limit below is also a place where naive intuition breaks — "instant step", "one giant cap", "far placement" — so walking them turns silent traps into things the reader has already seen fail. A derivation the reader can extrapolate past its edges is one they truly own; one that stops at the tidy middle case leaves them stranded the first time reality hands them a corner.

• $\Delta t\to 0$ (instant step). From Step 2, $V_L=L\Delta I/\Delta t\to \infty$: an ideal instantaneous step gives infinite droop through any inductance. Real signals have finite rise time — that finite $\Delta t$ is your only friend.
• $C\to \infty$ (one giant cap). Step 5 says droop $\to 0$ — tempting! But a bigger physical cap has larger $ESL$, so Step 7 gives $f_0\to$ low. It is inductive at GHz and useless for the ns spike. More farads ≠ faster.
• $C\to 0$ / far placement. No local charge, or charge behind extra trace inductance: the fast spike is served only by the villainous wire ⇒ full $Ldi/dt$ droop. This is why placement close to the die matters.
• $\omega \to 0$ (DC / steady state). $\frac{1}{\omega C}\to \infty$, $\omega ESL\to 0$: the cap blocks DC entirely. Steady current is handled by plain resistance ($V=IR$), not by caps — a different regime.
• Resonant frequencies between caps. Where one cap has gone inductive and the next is still capacitive, they can form an LC tank with a nasty impedance peak. This is why the hierarchy is engineered, not just "add many caps".

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The one-picture summary

Everything above compresses into one figure: the decoupling hierarchy, where each cap covers a frequency band, and their combined impedance stays under the target across the whole range. Bulk caps hold the low frequencies (slow droop), MLCCs the middle, on-die caps the fastest ns spikes — the closer the cap, the lower its inductance, the faster the event it can catch.

This ties back to the Power Delivery Network (PDN), where the whole delivery path — regulator, board, package, die — is engineered to keep the total impedance low across every frequency the chip can excite (including the DVFS operating points).

Recall Feynman: the whole walkthrough in plain words

A thirsty kid (the chip) gulps water in sudden bursts. The tap is far away down a long pipe, and moving water already in the pipe hates to speed up suddenly — that "hate to change" is the wire's inductance, and it's why the pressure at the cup drops the faster the kid gulps (not the more he drinks). So we set a cup of water right beside the kid: the capacitor. When he gulps, the cup empties first and holds the pressure up. How big must the cup be? Big enough to give the gulp of water ($\Delta I\Delta t$) while the pressure drops no more than allowed ($\Delta V_{max}$) — that's $C\ge \Delta I\Delta t/\Delta V_{max}$. But a real cup has a little straw of its own; sip fast enough and the straw (the cap's own $ESL$) chokes — that choke point is the self-resonant frequency $f_0$. One giant tank is slow to empty through its wide neck; a tiny cup reacts instantly but runs dry. So we keep several cup sizes at several distances: small-and-close for lightning gulps, big-and-far for the slow thirst.

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Connections

• 6.4.09 Voltage droop and decoupling capacitors (Hinglish)
• Power Delivery Network (PDN)
• Parasitic inductance and ESL/ESR
• di-dt and simultaneous switching noise
• Clock timing margin and Vmin
• Dynamic voltage and frequency scaling (DVFS)
• LC resonance and impedance