Visual walkthrough — Voltage droop and decoupling capacitors

6.4.9 · D2 · Hardware › Power, Thermal & Reliability › Voltage droop and decoupling capacitors

Yahan kuch bhi assume nahi kiya gaya hai. Agar aapne kabhi $\frac{dV}{dt}$, "impedance", ya "resonance" nahi dekha, toh aap inse milenge — apne-apne diagram mein, us order mein jisme aapko zaroorat hai.

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Step 1 — Asal mein kya maanga ja raha hai: charge, time par deliver ho

KYA. Ek chip ek bada bheed-bhaad wala system hai, bahut saare chote-chote switches ka. Jab unme se bahut saare ek saath flip karte hain, toh chip ko achanak ek current ka burst chahiye hota hai. Current ka matlab hai "charge per second flow hona". Toh asal request yeh hai: ek bahut kam time mein ek bucket of charge deliver karo.

YAH KYON SHURU KAREIN. Kisi bhi formula se pehle, yeh clear karna zaroori hai ki "droop" aakhir kis cheez ki failure hai. Yeh charge ko itni tezi se deliver na kar paane ki failure hai. Baad ki saari cheezein usi ek sentence ki accounting hai.

TASVEER. Figure dekho. Left side par hai ek door ka power supply. Right side par hai chip (load). Dono ke beech ek wire hai — jaan-bujhkar lamba dikhaya gaya hai. Chip par amber burst aisa dikhata hai ki achanak demand aa gayi.

Symbol $\frac{dQ}{dt}$ scary nahi hai: yeh charge-versus-time graph ka slope hai — steep slope matlab charge tezi se move ho raha hai, yaani bada current.

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Step 2 — Wire kyun ladaai karta hai: inductance aur $L\frac{di}{dt}$

KYA. Supply se chip tak ka lamba wire ek free connection nahi hai. Har wire mein inductance hoti hai, likha jaata hai $L$, henries mein measure hota hai. Inductance ek wire ki apna current badlne ki na-chahhat hai — jaise pipe mein pehle se beh raha paani ka bhaari pan.

YAH TOOL KYU AUR ABHI KYU. Hume yeh samjhaana hai ki ek supply jo "average ke lihaz se kaafi badi hai" woh bhi instantly respond kyun nahi kar sakti. Resistance ($V=IR$) se yeh explain nahi hoga: resistance ko parwah hai kitna current ka, na ki kitni jaldi ka. Woh quantity jo jaldi-jaldi-pan ko penalize karti hai woh hai inductance, law $V_L=L\frac{di}{dt}$ ke zariye. Toh hum $L$ ka sahara theek isliye lete hain kyunki problem ek tez change ke baare mein hai, aur $\frac{di}{dt}$ "current kitni tezi se badal raha hai" ka mathematical naam hai.

TASVEER. Current step ko ek ramp ke roop mein dikhaya gaya hai jo $0$ se $\Delta I$ tak bahut kam time $\Delta t$ mein chadta hai. Woh ramp jitna steep hoga, inductor utna hi zyada voltage wapas phenkta hai.

$$V_L=\underset{\begin{array}{c}\text{wire’s}\\ \text{inductance}\end{array}}{\underbrace{L}}\cdot \underset{\begin{array}{c}\text{slope of the}\\ \text{current ramp}\end{array}}{\underbrace{\frac{di}{dt}}}$$

• $L$ — wire ki geometry ki ek fixed property. Zyada lamba / patla loop ⇒ bada $L$.
• $\frac{di}{dt}$ — amber ramp kitna steep hai. Same $\Delta I$ lekin aadhe time mein ⇒ droop double ho jata hai.

Yeh $di/dt$ problem hai, aur yahan $L$ delivery path ki parasitic inductance hai.

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Step 3 — Rescue: chip ke paas hi ek charge ka bucket rakho

KYA. Agar door ka wire apna current itni tezi se ramp nahi kar sakta, toh hum chip ke millimetres paas ek local charge reservoir rakhte hain: ek capacitor, $C$. Pehle nanoseconds mein capacitor apne aap ko chip mein khaali karta hai, aur dheema wire tab tak free hai jab tak woh catch up karta hai.

KYU. Hum Step 2 ke villain ko physically bypass kar rahe hain. Woh charge jo pehle se load ke paas baitha hai, use lamba inductive wire nahi travel karna padta, isliye uska $L$ koi khaas mayne nahi rakhta. Speed proximity se aati hai, fatter supply se nahi.

TASVEER. Same layout jaise Step 1 mein, lekin ab chip ke bilkul paas ek capacitor hai ek choti low-inductance loop par. Amber arrows dikhate hain charge cap se nikal raha hai (fast, short path) jabki wire ka current abhi bhi aaram se ramp up kar raha hai.

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Step 4 — "$Q=CV$" ko droop equation mein badlo

KYA. Hum ek number chahte hain — voltage kitni neeche jaati hai jab sirf capacitor chip ko feed karta hai. Shuru karo $Q=CV$ se aur poochho ki jab charge nikalti hai toh $V$ kaise move karta hai.

DIFFERENTIATE KYU. $Q=CV$ ek static statement hai. Chip ki demand ek changing cheez hai. Ek changing charge ko changing voltage se connect karne ke liye hum differentiate karte hain — differentiation exactly woh tool hai jo "total stored" ko "rate of change" mein badalta hai.

$$i_C=\frac{dQ}{dt}=C\frac{dV}{dt}$$

• $i_C$ — yahan passive-sign convention mein likha gaya hai: $i_C$ woh current hai jo capacitor ke $+$ terminal mein flow kar raha hai, aur $\frac{dV}{dt}$ same $+/-$ reference se measure hoti hai. Jab cap charge up hota hai, $\frac{dV}{dt}>0$ aur $i_C>0$.
• $\frac{dV}{dt}$ — cap ki voltage kitni tezi se badal rahi hai.

TASVEER. Cap ki voltage rail se start hoti hai aur thodi si neeche khisakti hai jab woh current deliver karta hai; current pulse ka area woh charge hai jo usne di.

Ab pure spike par jo charge nikla use add up karo (integrate karo). Integration ka matlab hai "saare chote-chote charge bits $idt$ jodo". $\Delta V$ ko voltage drop ki magnitude manke aur $i(t)$ ko cap ke source kiye current ki magnitude manke:

$$\Delta V=\frac{1}{C}\int idt\underset{\begin{array}{c}\text{rectangular}\\ \text{pulse}\end{array}}{\approx }\frac{\stackrel{\text{total charge }Q\text{ delivered}}{\overbrace{\Delta I\cdot \Delta t}}}{C}$$

• $\approx$ assume karta hai constant-current (rectangular) pulse: current $\Delta I$ poore duration $\Delta t$ tak flat rakha, isliye $\int idt=\Delta I\cdot \Delta t$ exactly. Real spike ki apni shape hoti hai, lekin yeh rectangle standard worst-case bookkeeping hai — yeh ek ramp wale spike ke liye charge ko over-estimate karta hai, jo ek safe cap size deta hai.
• $\Delta I\cdot \Delta t$ — chip ke current pulse ka size times kitna woh tika = coulombs jo cap ne hand over kiye.
• $C$ se divide karo (coulombs per volt) ⇒ volts jo kho gaye. Bada $C$ ⇒ chota droop. Yeh single line hi poora reason hai ki capacitors fix kyun hain.

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Step 5 — Capacitor size karo (pehla boxed result)

KYA. Hume ek droop budget allow hai: voltage zyada se zyada $\Delta V_{max}$ tak hi sag kar sakti hai, phir woh $V_{min}$ pe aa jaati hai aur chip galat bits banata hai. Step-4 formula mein $\Delta V\le \Delta V_{max}$ impose karo aur $C$ ke liye solve karo.

$C$ KE LIYE KYU SOLVE. Step 4 ne droop ko output ke roop mein diya tha ek baar $C$ pata chalne par — lekin engineer ka asli sawaal ulta hai: "jo droop main kabhi exceed nahi karna chahta, uske liye minimum cap kya hai jo guarantee de?" Toh hum $\Delta V_{max}$ ko ek fixed limit maante hain, use $\Delta V$ ki jagah substitute karte hain, aur inequality ko rearrange karke $C$ akele ek side par le aate hain. Algebraically $C$ ko isolate karna ek description of droop ko ek design rule mein badal deta hai — ek threshold jo chosen cap ko paar karna hi hoga. Inequality direction ($\ge$) bachi rehti hai kyunki $C$ denominator mein hai, toh bada $C$ droop ko sirf aur chhota hi kar sakta hai — safely budget se neeche.

$$\Delta V=\frac{\Delta I\Delta t}{C}\le \Delta V_{max}⟹\boxed{C\ge \frac{\Delta I\cdot \Delta t}{\Delta V_{max}}}$$

• Numerator = woh charge jo aapko supply karna hai.
• Denominator = woh volts jo aap supply karte waqt khoone ko taiyaar hain.

TASVEER. Same spike ke liye do droop curves: ek chota cap red $V_{min}$ line ke neeche jaata hai (failure); ek sahi size wala cap uske upar rehta hai.

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Step 6 — Pakda: ek real capacitor thoda inductor bhi hota hai

KYA. Koi bhi physical capacitor pure nahi hota. Uske leads aur plates ek choti si series inductance $ESL$ aur resistance $ESR$ add karte hain. Isliye current ke against capacitor ka opposition — uska impedance $Z$ — teen parts ka sum hota hai.

IMPEDANCE KYU INTRODUCE KAREIN. Steps 4–5 ne assume kiya ki cap hamesha ready hai. Lekin cap ke $ESL$ ka matlab hai ki kaafi high frequency par woh bhi internally $Ldi/dt$ villain se pareshan ho jaata hai. Yeh dekhne ke liye ki woh kiyon frequencies par kaam aata hai, hume ek aisi quantity chahiye jo opposition-versus-frequency measure kare: woh hai impedance $Z(\omega )$, jahan $\omega =2\pi f$ angular frequency hai (har second mein kitne radians ka wiggle guzarta hai).

$$Z_{cap}(\omega )=\underset{\text{flat floor}}{\underbrace{ESR}}+\underset{\begin{array}{c}+\text{imaginary,}\\ \text{grows with }f\end{array}}{\underbrace{j\omega ESL}}\underset{\begin{array}{c}-\text{imaginary,}\\ \text{shrinks with }f\end{array}}{\underbrace{-\frac{j}{\omega C}}}$$

• Capacitive term ko is tarah likha gaya hai, $\frac{1}{j\omega C}$, lekin note karo $\frac{1}{j}=-j$, toh $\frac{1}{j\omega C}=-\frac{j}{\omega C}$. Yeh ek negative-imaginary (capacitive) reactance hai.
• $j\omega ESL$ positive-imaginary (inductive) reactance hai. Dono imaginary parts ke opposite sign hain, isliye woh ek frequency par cancel ho jaate hain — aur yahi cancellation agla step samjhata hai.
• $j$ bas ek bookkeeping tag hai matlab "yeh part 90° out of step push karta hai"; opposite signs ki wajah se inductive aur capacitive effects subtract hote hain, add nahi.
• $ESR$ — ek fixed real resistive floor.
• $\frac{1}{\omega C}$ — capacitive part ki magnitude; low $f$ par bahut bada, high $f$ par bahut chota.
• $\omega ESL$ — inductive part ki magnitude; low $f$ par bahut chota, high $f$ par bahut bada.

TASVEER. Classic V-shaped impedance curve log axes par: capacitive slope gir raha hai, inductive slope chadh raha hai, ek bottom par milte hain jahan dono cancel ho jaate hain.

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Step 7 — V ka bottom: self-resonant frequency

KYA. Do competing terms ki magnitude ek special frequency par equal hoti hai — self-resonant frequency $f_0$. Iske neeche cap capacitive hai (achha). Iske upar, $ESL$ jeet jaata hai aur "capacitor" ek inductor ki tarah behave karta hai — decoupling ke liye bekaar.

KYU. Dono reactance magnitudes ko equal set karo, $\frac{1}{\omega C}=\omega ESL$ (woh crossover jahan opposite-sign imaginary parts cancel hote hain), aur solve karo — woh frequency milti hai jahan impedance sirf $ESR$ par bottom out karta hai. Yeh LC resonance hai.

$$\frac{1}{{\omega }_{0}C}={\omega }_{0}ESL⟹\boxed{f_0=\frac{1}{2\pi \sqrt{ESL\cdot C}}}$$

• Bada $C$ ya bada $ESL$ ⇒ neecha $f_0$ ⇒ cap pehle hi "inductive" ho jaata hai.

TASVEER. Same V-curve, ab $f_0$ minimum par marked hai aur floor $ESR$ label hai; ek shaded amber band left side par useful (capacitive) region dikhata hai.

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Step 8 — Edge & degenerate cases (koi bhi scenario mat chhodna)

LIMITS KYU COVER KAREIN. Koi formula tabhi trustworthy lagta hai jab tum use extremes par bhi behave karte dekho. Neeche har limit ek aisi jagah bhi hai jahan naive intuition break hoti hai — "instant step", "ek bada cap", "dur placement" — toh inhe walk karna silent traps ko un cheezoon mein badal deta hai jo reader ne fail hote pehle hi dekh liye. Ek derivation jise reader apni limits se aage bhi extrapolate kar sake woh sach mein unka apna hai; jo sirf tidy middle case par ruk jaaye woh unhe pehli baar reality corner dene par phansa chhod deta hai.

• $\Delta t\to 0$ (instant step). Step 2 se, $V_L=L\Delta I/\Delta t\to \infty$: ek ideal instantaneous step kisi bhi inductance ke zariye infinite droop deta hai. Real signals ki finite rise time hoti hai — woh finite $\Delta t$ hi tumhara dost hai.
• $C\to \infty$ (ek bada cap). Step 5 kehta hai droop $\to 0$ — tempting! Lekin ek physically bada cap ka $ESL$ bhi bada hota hai, isliye Step 7 deta hai $f_0\to$ low. Woh GHz par inductive hai aur ns spike ke liye bekaar. Zyada farads ≠ tezi.
• $C\to 0$ / dur placement. Koi local charge nahi, ya extra trace inductance ke peeche charge: fast spike ko sirf villain wire serve karta hai ⇒ poora $Ldi/dt$ droop. Isliye die ke paas placement matter karti hai.
• $\omega \to 0$ (DC / steady state). $\frac{1}{\omega C}\to \infty$, $\omega ESL\to 0$: cap DC ko poori tarah block karta hai. Steady current plain resistance se handle hoti hai ($V=IR$), caps se nahi — yeh ek alag regime hai.
• Caps ke beech resonant frequencies. Jahan ek cap inductive ho gaya aur agla abhi capacitive hai, woh ek nasty impedance peak ke saath ek LC tank form kar sakte hain. Isliye hierarchy engineered hoti hai, bas "bahut saare caps daal do" nahi.

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Ek tasveer mein sab kuch

Upar ki saari cheezein ek figure mein compress ho jaati hain: decoupling hierarchy, jahan har cap ek frequency band cover karta hai, aur unka combined impedance poore range mein target ke neeche rehta hai. Bulk caps low frequencies (slow droop) hold karte hain, MLCCs middle, on-die caps fastest ns spikes — cap jitna paas, uski inductance utni kam, aur woh utni tez event catch kar sakta hai.

Yeh Power Delivery Network (PDN) se juda hai, jahan poora delivery path — regulator, board, package, die — engineer kiya jaata hai taaki total impedance har us frequency par low rahe jo chip excite kar sake (including DVFS operating points).

Recall Feynman: plain words mein poora walkthrough

Ek pyaasa bachcha (chip) paani ke achanak jhake mein peeta hai. Nal door hai ek lambi pipe ke neeche, aur pipe mein pehle se beh raha paani achanak tezi pakadna pasand nahi karta — yeh "change karna nahi chahna" wire ki inductance hai, aur isliye cup par pressure utna zyada girta hai jitna tezi se bachcha ghoontta hai (utna nahi jitna zyada peeta hai). Toh hum bachche ke bilkul paas paani ka ek cup rakh dete hain: capacitor. Jab woh ghoontta hai, cup pehle khaali hota hai aur pressure upar rakhta hai. Cup kitna bada hona chahiye? Itna bada ki paani ki ghoontt ($\Delta I\Delta t$) de sake jabki pressure zyada se zyada allowed se neeche na jaaye ($\Delta V_{max}$) — wahi hai $C\ge \Delta I\Delta t/\Delta V_{max}$. Lekin ek real cup ka apna chota straw hota hai; itni tezi se peeo aur straw (cap ka apna $ESL$) choke ho jaata hai — woh choke point self-resonant frequency $f_0$ hai. Ek bada tank apni wide neck se dheere khaali hota hai; ek chota cup fauran react karta hai lekin jaldi sookh bhi jaata hai. Toh hum kai cup sizes kai distances par rakhte hain: fast lightning gulps ke liye small-and-close, slow thirst ke liye big-and-far.

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Connections

• 6.4.09 Voltage droop and decoupling capacitors (Hinglish)
• Power Delivery Network (PDN)
• Parasitic inductance and ESL/ESR
• di-dt and simultaneous switching noise
• Clock timing margin and Vmin
• Dynamic voltage and frequency scaling (DVFS)
• LC resonance and impedance