Voltage droop and decoupling capacitors: Question bank

Reminder of the two laws everything reduces to:

Symbols you need before the traps

Before you can reason about the traps, four symbols must be earned. Read this block once; the figures below make each one visual.

Definition Charge

$Q$ , and where $Δ V = Δ I Δ t / C$ comes from $Q$ here means electric charge — the amount of "electric water" a capacitor holds, measured in coulombs. (In resonance discussions the letter $Q$ sometimes means "quality factor"; not here — on this page $Q$ is always charge.) A capacitor obeys $Q = C V$ : charge equals capacitance times voltage. If the voltage changes by $Δ V$ , the stored charge changes by $Δ Q = C Δ V .$ Now, where does that extra charge go? It flows out as current. Current is charge per second, so over a spike of duration $Δ t$ carrying current $Δ I$ , the charge delivered is $Δ Q = Δ I \cdot Δ t .$ Set the two expressions for $Δ Q$ equal — the charge the cap loses is the charge the load takes: $C Δ V = Δ I \cdot Δ t \Rightarrow Δ V = \frac{Δ I \cdot Δ t}{C} .$ This is the charge-depletion droop. Bigger $C$ ⇒ smaller sag. Look at the top panel of the figure: the cap is a bucket that empties by $Δ Q$ .

Definition Reactance: why

$X_{C} = 1/ (ω C)$ falls and $X_{L} = ω L$ rises First, angular frequency $ω = 2 π f$ : ordinary frequency $f$ counts cycles per second, and one cycle is $2 π$ radians, so $ω$ is just $f$ scaled by $2 π$ (radians per second). The reactance formulas come out cleaner in $ω$ . Reactance is an element's opposition to an alternating current — its "AC resistance" at frequency $ω$ . Derive both from the two laws we already have:

Inductor. For a sine current $i = I_{0} sin (ω t)$ , the rate of change is $d i / d t = ω I_{0} cos (ω t)$ . Plug into $V_{L} = L d i / d t$ : the voltage amplitude is $ω L I_{0}$ . So opposition $= \frac{voltage}{current} = ω L$ . Call it $X_{L} = ω L$ . Faster wiggling ⇒ bigger $d i / d t$ ⇒ more opposition. $X_{L}$ rises with $ω$ .
Capacitor. From $i_{C} = C d V / d t$ , a sine voltage $V = V_{0} sin (ω t)$ gives current amplitude $ω C V_{0}$ . So opposition $= \frac{V _{0}}{ω C V _{0}} = \frac{1}{ω C}$ . Call it $X_{C} = \frac{1}{ω C}$ . Faster wiggling ⇒ the cap barely charges before the direction flips ⇒ it passes current easily ⇒ less opposition. $X_{C}$ falls with $ω$ . These two are the machinery behind everything: at low $ω$ the cap ( $X_{C}$ ) dominates, at high $ω$ the inductance ( $X_{L}$ ) dominates.

Definition Putting it together:

$Z_{P D N} (ω) = R + j (ω L - \frac{1}{ω C})$ and $f_{0}$ $Z_{P D N}$ is the PDN impedance: the total opposition the whole power delivery network shows to a wiggling current at frequency $ω$ . Resistance and reactance don't simply add — the reactive voltage is a quarter-cycle out of step with the resistive one, so we track them on perpendicular axes (the " $j$ " just marks the perpendicular, reactive axis). For a series resistance $R$ , inductance $L$ , capacitance $C$ : $Z_{P D N} (ω) = R + j (ω L - \frac{1}{ω C}) = E S R + j (ω E S L - \frac{1}{ω C}) .$ The magnitude (the number that actually sets droop, $Δ V = Δ I ∣ Z_{P D N} ∣$ ) is $∣ Z_{P D N} ∣ = R^{2} + (ω L - \frac{1}{ω C})^{2} .$ The reactive part $ω L - 1/ (ω C)$ cancels to zero when $ω L = 1/ (ω C)$ , leaving only $R$ — that is the impedance minimum, and solving for frequency gives the self-resonant frequency $f_{0} = \frac{1}{2 π L C} = \frac{1}{2 π E S L \cdot C} .$ Below $f_{0}$ the $- 1/ (ω C)$ term wins (capacitive, helps hold voltage); above $f_{0}$ the $+ ω L$ term wins (inductive, stops helping). See Parasitic inductance and ESL/ESR and LC resonance and impedance.

The bucket picture and the $∣ Z ∣$ -vs-frequency dip (with its $f_{0}$ ) are drawn here:

Figure — Voltage droop and decoupling capacitors

The perpendicular-axes ("phasor") picture below shows why $R$ and the reactance add as legs of a right triangle, and how the reactive leg collapses at $f_{0}$ — study it before the "Spot the error" anti-resonance item:

And the anti-resonance figure — the impedance spike that appears when a bulk cap and a ceramic cap are placed in parallel — is the visual for the last "Spot the error" and the anti-resonance edge case:

True or false — justify

A steady 100 A draw is more dangerous for droop than a 10 A step that happens in 1 ns.

False. Steady current makes only the

I R

drop, which is small and predictable; the 1 ns step has a huge

d i / d t

, and

V_{L} = L d i / d t

is the transient that pushes

V

toward

V_{min}

. It's the rate, not the magnitude.

Doubling the decoupling capacitance always halves the worst-case droop.

False. It halves the charge-depletion droop

Δ V = Δ I Δ t / C

, but how you double it matters. A single physically bigger cap has higher

E S L

, lowering its

f_{0} = 1/ (2 π E S L C)

, so at the fastest spikes it turns inductive. Paralleling two identical caps instead both doubles

C

and halves

E S L

(two inductances in parallel), keeping

f_{0}

and helping at high frequency — so the outcome depends entirely on the method. See Parasitic inductance and ESL/ESR.

A capacitor above its self-resonant frequency

f_{0}

still provides some help, just less.

False in the useful sense. Above

f_{0}

the inductive reactance

X_{L} = ω E S L

dominates over

X_{C} = 1/ (ω C)

, so the cap behaves like an inductor — its impedance rises with frequency, and it actively fails to hold voltage at those fast events.

Voltage droop can only pull the rail down, never push it up.

False. A current step down (load suddenly stops drawing) makes

d i / d t

negative, so

V_{L} = L d i / d t

flips sign and the rail overshoots above nominal — the same LC ringing mechanism, just the other polarity.

If two capacitors have identical capacitance, they behave identically in a PDN.

False. Package size,

E S L

, and

E S R

differ, so their

f_{0} = 1/ (2 π E S L C)

and minimum impedance differ. Identical

C

does not mean identical frequency behaviour.

Placing a decoupling cap 2 cm away instead of 2 mm away changes nothing because it's the same electrical net.

False. Extra trace length adds loop inductance between cap and die; that inductance sits in series with the cap, slowing its charge delivery exactly when the fast spike needs it. Proximity is the whole point.

The voltage regulator far away can simply be made faster to eliminate droop.

False. However fast the regulator's control loop, the current still has to travel through the board inductance

L

, and

L

physically resists rapid current change. Local charge (a cap) is the only thing near enough to react in nanoseconds.

Lowering the supply voltage via DVFS makes droop irrelevant.

False. Lowering

V

also shrinks the gap to

V_{min}

: the absolute droop budget

Δ V_{ma x} = V_{n o mina l} - V_{min}

gets smaller, so the same droop that was safe at 1.0 V can fail at 0.7 V. DVFS often makes droop more critical.

Spot the error

"Droop is

Δ V = Δ I \cdot Z_{P D N}

, so if the PDN impedance

Z_{P D N}

is small at DC we are safe at all frequencies."

The error is treating

Z_{P D N}

as one number. From

Z_{P D N} (ω) = R + j (ω L - 1/ (ω C))

it clearly depends on frequency; a PDN can be tiny at DC yet spike at its resonance. You must keep

∣ Z_{P D N} (ω) ∣

low across the whole band the current excites.

V_{L} = L d i / d t

, so we should maximize

L

near the load to store more energy."

Backwards.

L

near the load is the villain — it turns fast

d i / d t

into a large droop voltage. You minimize series

L

between cap and die, not maximize it.

"Self-resonant frequency

f_{0} = 1/ (2 π E S L \cdot C)

, so a bigger cap has a higher

f_{0}

Wrong direction.

C

is under the square root in the denominator, so larger

C

lowers

f_{0}

. That's precisely why big bulk caps cover only low frequencies.

"At resonance the impedance is maximum, so that frequency is the most dangerous."

For one series R-L-C cap — where

R

is its

E S R

and

L

is its

E S L

— resonance is where the reactive term

ω E S L - 1/ (ω C)

cancels, so

∣ Z ∣

is minimum (

= E S R

); it's actually the cap's best point. The dangerous maximum is the anti-resonance between two cap banks (bulk vs ceramic) in the PDN network — see the anti-resonance figure above.

"Since

Q = C V

(with

Q

the stored electric charge), a charged cap delivers all its charge instantly, so response time doesn't matter."

The delivery speed is limited by the loop inductance in series with the cap, not by

Q

alone.

i_{C} = C d V / d t

gives the current, but the surrounding

E S L

and trace

L

cap how fast that current can rise.

"On-die caps are tiny (pF), so they can't matter compared to the 100 µF bulk cap."

Capacitance size ≠ usefulness. The on-die cap has near-zero inductance and is physically closest, so it's the only thing fast enough for the ns-scale spike; the huge bulk cap is too far/inductive to respond that quickly.

Why questions

Why does the inductor, not the resistor, dominate the worst transient droop?

Because

V_{L} = L d i / d t

scales with the rate of current change, and modern cores slew tens of amps in a nanosecond, giving enormous

d i / d t

. See di-dt and simultaneous switching noise.

Why do we need a hierarchy of capacitors rather than one perfect capacitor?

No single cap has low impedance across all frequencies — each has one resonance

f_{0}

. Stacking bulk, ceramic, and on-die caps lets each cover its own band so

∣ Z_{P D N} (ω) ∣

stays low everywhere.

Why does putting caps close to the power pins matter physically?

Distance adds series loop inductance, and that inductance is exactly what slows charge delivery. Close placement minimizes the loop, letting current rise fast enough to catch the spike.

Why can a droop event corrupt data even if power never fully cuts out?

V

dips below

V_{min}

, transistors switch too slowly and miss the clock timing margin, latching wrong bits — a logic error, not a power-off.

Why does the far regulator sitting "behind a big

L

" force us to use local charge?

The inductance forces the regulator's current to ramp gradually; during that ramp it cannot supply the sudden demand, so a local capacitor must bridge the gap in the first nanoseconds. See Power Delivery Network (PDN).

Why is

E S R

(not zero impedance) the floor of a good decoupling cap?

At resonance the reactive term

ω E S L - 1/ (ω C)

cancels, leaving only the resistive

E S R

. A little

E S R

is even helpful — it damps the LC ringing that would otherwise peak sharply.

Edge cases

What happens to droop when

Δ t \to 0

(an idealized instantaneous current step)?

The charge-depletion droop

Δ I Δ t / C

shrinks toward zero, but

d i / d t \to \infty

, so the inductive droop

L d i / d t

explodes. The inductive term, not the capacitive one, sets the limit for infinitely fast steps.

What is the droop for a current draw that is large but unchanging (

Δ I = 0

, i.e. the current level is high yet steady)?

Zero transient droop — with no change there is no

d i / d t

and no capacitor discharge; only the static

I R

drop remains. Confirms droop is about change, not the standing current level.

E S L = 0

(a hypothetical perfect cap), does the cap work at all frequencies?

In that ideal it never turns inductive, so its capacitive reactance

X_{C} = 1/ (ω C)

keeps falling with rising frequency and it helps at every frequency. Real caps always have some

E S L

, so this ideal is unreachable — which is why hierarchy exists.

What happens at the exact anti-resonance between a bulk cap and a ceramic cap?

The bulk cap's inductance resonates with the ceramic cap's capacitance, creating a sharp impedance peak — a frequency where the PDN is unexpectedly weak (see the anti-resonance figure above). Careful cap selection and

E S R

damping flatten this peak. See LC resonance and impedance.

At DC (zero frequency), which PDN element sets the voltage drop, and why?

Pure resistance

R

: at

ω = 0

the inductive reactance

X_{L} = ω L = 0

(fully passes steady current) and the capacitive reactance

X_{C} = 1/ (ω C) \to \infty

(blocks steady current), so only

V_{R} = I R

survives.

Recall One-line self-test before you leave

Can you, in one sentence each, say (a) why magnitude ≠ danger, (b) why one cap ≠ enough, and (c) why distance = inductance? If any stalls, reread that trap above.

Connections

Voltage droop and decoupling capacitors
Power Delivery Network (PDN)
Parasitic inductance and ESL/ESR
di-dt and simultaneous switching noise
Clock timing margin and Vmin
Dynamic voltage and frequency scaling (DVFS)
LC resonance and impedance