Voltage droop and decoupling capacitors: Question bank

6.4.9 · D5 · Hardware › Power, Thermal & Reliability › Voltage droop and decoupling capacitors

Do laws ka reminder jisme sab kuch reduce hota hai:

Traps se pehle zaruri symbols

Traps ke baare mein reason karne se pehle, chaar symbols samajhne zaroori hain. Is block ko ek baar padho; neeche ke figures har ek ko visual banate hain.

Definition Charge

$Q$ , aur $Δ V = Δ I Δ t / C$ kahan se aata hai $Q$ yahan electric charge hai — woh amount of "electric water" jo ek capacitor hold karta hai, coulombs mein measure hota hai. (Resonance discussions mein $Q$ ka matlab kabhi kabhi "quality factor" hota hai; yahan nahi — is page par $Q$ hamesha charge hai.) Ek capacitor $Q = C V$ follow karta hai: charge equals capacitance times voltage. Agar voltage $Δ V$ se change ho, toh stored charge isse change hoga $Δ Q = C Δ V .$ Ab, woh extra charge kahan jaata hai? Woh current ke roop mein baahir flow karta hai. Current hai charge per second, toh $Δ t$ duration ki spike jo $Δ I$ current carry karti hai, usme deliver hone wala charge hai $Δ Q = Δ I \cdot Δ t .$ $Δ Q$ ke dono expressions ko equal karo — cap jo charge khota hai woh load jo charge leta hai: $C Δ V = Δ I \cdot Δ t \Rightarrow Δ V = \frac{Δ I \cdot Δ t}{C} .$ Yahi charge-depletion droop hai. Bada $C$ ⇒ chhota sag. Figure ke top panel dekho: cap ek bucket hai jo $Δ Q$ se khaali ho jaata hai.

Definition Reactance: kyun

$X_{C} = 1/ (ω C)$ girta hai aur $X_{L} = ω L$ badhta hai Pehle, angular frequency $ω = 2 π f$ : ordinary frequency $f$ cycles per second count karta hai, aur ek cycle $2 π$ radians hoti hai, toh $ω$ simply $f$ ko $2 π$ se scale kiya hua hai (radians per second). Reactance formulas $ω$ mein zyada clean nikalte hain. Reactance kisi element ki alternating current ke against opposition hai — uski "AC resistance" frequency $ω$ par. Dono ko un do laws se derive karo jo humne pehle se dekhe hain:

Inductor. Sine current $i = I_{0} sin (ω t)$ ke liye, rate of change hai $d i / d t = ω I_{0} cos (ω t)$ . $V_{L} = L d i / d t$ mein plug karo: voltage amplitude hai $ω L I_{0}$ . Toh opposition $= \frac{voltage}{current} = ω L$ . Ise $X_{L} = ω L$ kaho. Tezi se wiggling ⇒ bada $d i / d t$ ⇒ zyada opposition. $X_{L}$ $ω$ ke saath badhta hai.
Capacitor. $i_{C} = C d V / d t$ se, sine voltage $V = V_{0} sin (ω t)$ current amplitude $ω C V_{0}$ deta hai. Toh opposition $= \frac{V _{0}}{ω C V _{0}} = \frac{1}{ω C}$ . Ise $X_{C} = \frac{1}{ω C}$ kaho. Tezi se wiggling ⇒ cap direction flip hone se pehle muskil se charge hota hai ⇒ current aasaani se pass karta hai ⇒ kam opposition. $X_{C}$ $ω$ ke saath girta hai. Yahi do sab kuch ke peeche machinery hain: low $ω$ par cap ( $X_{C}$ ) dominate karta hai, high $ω$ par inductance ( $X_{L}$ ) dominate karta hai.

Definition Sab kuch milaana:

$Z_{P D N} (ω) = R + j (ω L - \frac{1}{ω C})$ aur $f_{0}$ $Z_{P D N}$ PDN impedance hai: woh total opposition jo poora power delivery network frequency $ω$ par wiggling current ko dikhata hai. Resistance aur reactance simply add nahi hote — reactive voltage resistive wale se quarter-cycle out of step hai, toh hum inhe perpendicular axes par track karte hain (" $j$ " simply perpendicular, reactive axis mark karta hai). Series resistance $R$ , inductance $L$ , capacitance $C$ ke liye: $Z_{P D N} (ω) = R + j (ω L - \frac{1}{ω C}) = E S R + j (ω E S L - \frac{1}{ω C}) .$ Magnitude (woh number jo actually droop set karta hai, $Δ V = Δ I ∣ Z_{P D N} ∣$ ) hai $∣ Z_{P D N} ∣ = R^{2} + (ω L - \frac{1}{ω C})^{2} .$ Reactive part $ω L - 1/ (ω C)$ zero cancel ho jaata hai jab $ω L = 1/ (ω C)$ , sirf $R$ bachta hai — yahi impedance minimum hai, aur frequency ke liye solve karne par milta hai self-resonant frequency $f_{0} = \frac{1}{2 π L C} = \frac{1}{2 π E S L \cdot C} .$ $f_{0}$ ke neeche $- 1/ (ω C)$ term jeet jaata hai (capacitive, voltage hold karne mein help karta hai); $f_{0}$ ke upar $+ ω L$ term jeet jaata hai (inductive, help karna band kar deta hai). Dekho Parasitic inductance and ESL/ESR aur LC resonance and impedance.

Bucket picture aur $∣ Z ∣$ -vs-frequency dip (apne $f_{0}$ ke saath) yahan drawn hai:

Figure — Voltage droop and decoupling capacitors

Perpendicular-axes ("phasor") picture neeche dikhata hai kyun $R$ aur reactance right triangle ki legs ki tarah add hote hain, aur kaise reactive leg $f_{0}$ par collapse hoti hai — "Spot the error" anti-resonance item se pehle ise padho:

Aur anti-resonance figure — woh impedance spike jo tab appear hoti hai jab ek bulk cap aur ek ceramic cap parallel mein place kiye jaate hain — aakhri "Spot the error" aur anti-resonance edge case ka visual hai:

True or false — justify karo

Ek steady 100 A draw, 10 A step se zyada dangerous hai droop ke liye jo 1 ns mein hota hai.

False. Steady current sirf

I R

drop banata hai, jo chhota aur predictable hai; 1 ns step mein bahut bada

d i / d t

hai, aur

V_{L} = L d i / d t

woh transient hai jo

V

V_{min}

ki taraf dhakelta hai. Yeh rate ke baare mein hai, magnitude ke baare mein nahi.

Decoupling capacitance double karna hamesha worst-case droop aadha kar deta hai.

False. Yeh charge-depletion droop

Δ V = Δ I Δ t / C

aadha karta hai, lekin kaise double karte ho yeh matter karta hai. Ek physically bada cap higher

E S L

rakha hai, jisse uski

f_{0} = 1/ (2 π E S L C)

lower ho jaati hai, toh sabse fast spikes par woh inductive ho jaata hai. Do identical caps parallel karna instead

C

double aur

E S L

aadha karta hai (do inductances parallel mein),

f_{0}

maintain rakhta hai aur high frequency par help karta hai — isliye outcome poori tarah method par depend karta hai. Dekho Parasitic inductance and ESL/ESR.

Apni self-resonant frequency

f_{0}

se upar ka capacitor abhi bhi kuch help karta hai, bas kam.

Useful sense mein False.

f_{0}

ke upar inductive reactance

X_{L} = ω E S L

X_{C} = 1/ (ω C)

par dominate karta hai, toh cap ek inductor ki tarah behave karta hai — uski impedance frequency ke saath badhti hai, aur woh actively un fast events par voltage hold karne mein fail hota hai.

Voltage droop rail ko sirf neeche pull kar sakta hai, upar push nahi kar sakta.

False. Current step down (load achanak draw karna band kar deta hai)

d i / d t

negative banaata hai, toh

V_{L} = L d i / d t

sign flip kar deta hai aur rail nominal se overshoot karta hai upar — wahi LC ringing mechanism, bas dusri polarity.

Agar do capacitors ki capacitance identical hai, toh woh PDN mein identically behave karte hain.

False. Package size,

E S L

, aur

E S R

differ karte hain, toh unka

f_{0} = 1/ (2 π E S L C)

aur minimum impedance differ karta hai. Identical

C

ka matlab identical frequency behaviour nahi hai.

2 mm ki jagah 2 cm door decoupling cap place karna kuch nahi badalta kyunki yeh same electrical net hai.

False. Extra trace length cap aur die ke beech loop inductance add karta hai; woh inductance cap ke series mein baith jaata hai, charge delivery exactly tab slow karta hai jab fast spike ko uski zaroorat hai. Proximity hi sab kuch hai.

Door ka voltage regulator simply tez banaya ja sakta hai droop khatam karne ke liye.

False. Regulator ka control loop kitna bhi fast ho, current ko abhi bhi board inductance

L

ke through travel karna padta hai, aur

L

physically rapid current change resist karta hai. Local charge (ek cap) hi woh akela cheez hai jo nanoseconds mein react karne ke liye kaafi paas hai.

DVFS ke zariye supply voltage lower karna droop ko irrelevant bana deta hai.

False.

V

lower karna

V_{min}

tak gap bhi chhota karta hai: absolute droop budget

Δ V_{ma x} = V_{n o mina l} - V_{min}

chhota ho jaata hai, toh wahi droop jo 1.0 V par safe tha 0.7 V par fail kar sakta hai. DVFS aksar droop ko zyada critical bana deta hai.

Spot the error

"Droop hai

Δ V = Δ I \cdot Z_{P D N}

, toh agar PDN impedance

Z_{P D N}

DC par small hai toh hum har frequency par safe hain."

Error yeh hai ki

Z_{P D N}

ko ek number maana ja raha hai.

Z_{P D N} (ω) = R + j (ω L - 1/ (ω C))

se clearly yeh frequency par depend karta hai; ek PDN DC par tiny ho sakta hai phir bhi apne resonance par spike kar sakta hai. Tumhe

∣ Z_{P D N} (ω) ∣

ko poore us band mein low rakhna hoga jise current excite karta hai.

V_{L} = L d i / d t

, toh hume load ke paas

L

maximize karna chahiye zyada energy store karne ke liye."

Ulta. Load ke paas

L

villain hai — yeh fast

d i / d t

ko bade droop voltage mein convert karta hai. Cap aur die ke beech series

L

minimize karo, maximize nahi.

"Self-resonant frequency

f_{0} = 1/ (2 π E S L \cdot C)

, toh bada cap higher

f_{0}

rakhta hai."

Galat direction.

C

denominator ke square root ke under hai, toh bada

C

f_{0}

lower karta hai. Yahi precisely wajah hai ki bade bulk caps sirf low frequencies cover karte hain.

"Resonance par impedance maximum hota hai, toh woh frequency sabse dangerous hai."

Ek series R-L-C cap ke liye — jahan

R

uska

E S R

hai aur

L

uska

E S L

hai — resonance wahan hai jahan reactive term

ω E S L - 1/ (ω C)

cancel hota hai, toh

∣ Z ∣

minimum hai (

= E S R

); yeh actually cap ka best point hai. Dangerous maximum anti-resonance hai do cap banks (bulk vs ceramic) ke beech PDN network mein — upar anti-resonance figure dekho.

"Kyunki

Q = C V

(jahan

Q

stored electric charge hai), ek charged cap apna saara charge instantly deliver karta hai, toh response time matter nahi karta."

Delivery speed cap ke series mein loop inductance se limit hoti hai, sirf

Q

se nahi.

i_{C} = C d V / d t

current deta hai, lekin surrounding

E S L

aur trace

L

cap karte hain ki woh current kitni tezi se rise kar sakta hai.

"On-die caps chhote hain (pF), toh woh 100 µF bulk cap ke compare mein matter nahi kar sakte."

Capacitance size ≠ usefulness. On-die cap ke paas near-zero inductance hai aur woh physically sabse paas hai, toh woh akela cheez hai jo ns-scale spike ke liye itna fast hai; woh huge bulk cap respond karne ke liye bahut door/inductive hai.

Why questions

Inductor kyun worst transient droop dominate karta hai, resistor kyun nahi?

Kyunki

V_{L} = L d i / d t

current change ki rate ke saath scale karta hai, aur modern cores ek nanosecond mein tens of amps slew karte hain, enormous

d i / d t

dete hain. Dekho di-dt and simultaneous switching noise.

Hume ek perfect capacitor ki jagah capacitors ki hierarchy kyun chahiye?

Koi bhi single cap har frequency par low impedance nahi rakhta — har ek ka ek resonance

f_{0}

hai. Bulk, ceramic, aur on-die caps stack karna har ek ko apna band cover karne deta hai taki

∣ Z_{P D N} (ω) ∣

har jagah low rahe.

Caps ko power pins ke paas physically rakhna physically kyun matter karta hai?

Distance series loop inductance add karta hai, aur wahi inductance charge delivery slow karti hai. Paas placement loop minimize karta hai, current ko itni tezi se rise karne deta hai ki spike pakad sake.

Droop event data corrupt kyun kar sakta hai agar power poori tarah cut out nahi hui?

Agar

V

V_{min}

ke neeche dip kare, transistors bahut dheeray switch karte hain aur clock timing margin miss kar dete hain, galat bits latch ho jaate hain — ek logic error, power-off nahi.

Door regulator "bade

L

ke peechhay" baithne ki wajah se hume local charge use kyun karna padta hai?

Inductance regulator ke current ko gradually ramp karne par force karti hai; us ramp ke dauran woh sudden demand supply nahi kar sakta, toh ek local capacitor pehle nanoseconds mein gap bridge karta hai. Dekho Power Delivery Network (PDN).

E S R

(zero impedance nahi) ek achhe decoupling cap ka floor kyun hai?

Resonance par reactive term

ω E S L - 1/ (ω C)

cancel hota hai, sirf resistive

E S R

bachta hai. Thoda

E S R

helpful bhi hai — yeh LC ringing ko damp karta hai jo otherwise sharply peak kar deta.

Edge cases

Δ t \to 0

hone par droop ka kya hota hai (ek idealized instantaneous current step)?

Charge-depletion droop

Δ I Δ t / C

zero ki taraf shrink karta hai, lekin

d i / d t \to \infty

, toh inductive droop

L d i / d t

explode karta hai. Inductive term, capacitive wala nahi, infinitely fast steps ki limit set karta hai.

Ek current draw ke liye droop kya hai jo bada hai lekin unchanging hai (

Δ I = 0

, yaani current level high hai phir bhi steady hai)?

Zero transient droop — koi change nahi toh koi

d i / d t

nahi aur koi capacitor discharge nahi; sirf static

I R

drop bachta hai. Confirm karta hai ki droop change ke baare mein hai, standing current level ke baare mein nahi.

Agar

E S L = 0

hota (ek hypothetical perfect cap), kya cap har frequency par kaam karta?

Us ideal mein woh kabhi inductive nahi hota, toh uski capacitive reactance

X_{C} = 1/ (ω C)

rising frequency ke saath girती rehti hai aur woh har frequency par help karta hai. Real caps mein hamesha kuch

E S L

hota hai, toh yeh ideal unreachable hai — isliye hierarchy exist karti hai.

Ek bulk cap aur ek ceramic cap ke beech exact anti-resonance par kya hota hai?

Bulk cap ki inductance ceramic cap ki capacitance ke saath resonate karti hai, ek sharp impedance peak banati hai — ek frequency jahan PDN unexpectedly weak hai (upar anti-resonance figure dekho). Careful cap selection aur

E S R

damping is peak ko flatten karte hain. Dekho LC resonance and impedance.

DC par (zero frequency), kaunsa PDN element voltage drop set karta hai, aur kyun?

Pure resistance

R

ω = 0

par inductive reactance

X_{L} = ω L = 0

(steady current fully pass karta hai) aur capacitive reactance

X_{C} = 1/ (ω C) \to \infty

(steady current block karta hai), toh sirf

V_{R} = I R

bachta hai.

Recall Jane se pehle ek-line self-test

Kya tum, ek sentence mein, keh sakte ho (a) kyun magnitude ≠ danger, (b) kyun ek cap ≠ enough, aur (c) kyun distance = inductance? Agar koi ruk jaaye, toh upar woh trap dobara padho.

Connections

Voltage droop and decoupling capacitors
Power Delivery Network (PDN)
Parasitic inductance and ESL/ESR
di-dt and simultaneous switching noise
Clock timing margin and Vmin
Dynamic voltage and frequency scaling (DVFS)
LC resonance and impedance