Voltage droop and decoupling capacitors: Worked examples

6.4.9 · D3 · Hardware › Power, Thermal & Reliability › Voltage droop and decoupling capacitors

Yeh deep-dive parent topic Voltage droop and decoupling capacitors ke har us case ko drill karta hai jo exam ya real board par aa sakta hai. Hum har jawab unhi do laws se build karte hain jo tumne already dekhe hain, lekin yahan hum un degenerate, limiting, aur sign cases ko pakdte hain jinhe parent note ne gloss over kar diya tha.

Koi bhi number likhne se pehle, har ek symbol ko plain words mein samjhao, jo hum use karte hain:

Definition Is page ka har symbol, use se pehle define kiya gaya

$Δ I$ — current kitna jump karta hai, amps (A) mein. Ek positive $Δ I$ ka matlab hai chip achanak zyada current maang rahi hai.
$Δ t$ — woh jump kitna time leta hai, seconds (s) mein. Chhota $Δ t$ = tez = zyada khatarnak.
$\frac{d i}{d t}$ — current-versus-time line ki slope: amps per second (A/s) mein. Graph par "rise over run" ke roop mein padho.
$Δ V$ — voltage rail ka resulting wobble, volts (V) mein. Droop ek negative $Δ V$ hota hai (rail sag jaati hai).
$V_{L}$ — woh voltage jo inductor par tab appear hoti hai jab uska current change ho raha hota hai, volts (V) mein. Yeh "villain" voltage hai jo ek fast edge ke dauran rail se chura leti hai.
$Q$ — electric charge, woh "electricity" ki matra jo ek capacitor store karta hai, coulombs (C) mein. Ek coulomb matlab ek amp ek second ke liye flow kare, isliye $Q = I \cdot t$ .
$L$ — wire/path ki inductance, henries (H) mein: path kitni strongly current mein change se ladti hai. Ise ek lambe pipe mein paani ki bhaari pan ke roop mein socho jo speed up ya slow down karna pasand nahi karta.
$C$ — decoupling cap ki capacitance, farads (F) mein: "cup of charge" kitna bada hai. Bada $C$ = gehri cup = usi charge ke liye chhota sag.
$R$ — resistance, ohms ( $Ω$ ) mein: woh steady voltage-per-amp toll jo ek wire hamesha leta hai, DC par bhi.
$E S R$ — Equivalent Series Resistance: ek real capacitor ke andar chhoti unavoidable resistance ( $Ω$ mein).
$E S L$ — Equivalent Series Inductance: ek real capacitor ke andar chhoti unavoidable inductance (H mein), uske apne leads/plates se.
$j$ — imaginary unit ( $j = - 1$ ; engineers $j$ likhte hain $i$ ki jagah taaki current se confuse na ho). Yeh ek bookkeeping symbol hai jo AC circuits mein $9 0^{\circ}$ phase shift track karta hai — tumhe ise kabhi "compute" nahi karna, sirf carry karna hai.

The scenario matrix

Is topic ka har problem is table ki ek cell hai. "Case class" = woh physical situation jo tumhe di gayi hai; "What is being tested" = woh single formula ya idea jo ise crack karta hai. Har row ko aise padho: "agar situation X hai, toh tool Y use karo."

#	Case class (tumhe di gayi situation)	What is being tested (use karne wala tool)	Example
A	Tumhe ek fast current step aur droop budget diya gaya hai, cap size puchha gaya hai	Sizing formula $C \geq Δ I Δ t /Δ V_{ma x}$	Ex 1
B	Current inductance se rise ho raha hai ( $d i / d t > 0$ )	$V_{L} = L d i / d t$ ek positive number deta hai → ek sag	Ex 2
C	Current inductance se fall ho raha hai ( $d i / d t < 0$ )	Same law; negative slope → negative $V_{L}$ → ek overshoot	Ex 3
D	Current constant hai (steady DC, $d i / d t = 0$ )	Inductor gayab ho jaata hai ( $V_{L} = 0$ ); sirf Ohm's $I R$ drop bachta hai — isliye yeh cell "IR-only" hai	Ex 4
E	Transition time zero ki taraf squeeze ho rahi hai ( $Δ t \to 0$ )	Limiting behaviour: droop $\to \infty$ , isliye caps local hone chahiye	Ex 5
F	Pucha gaya hai ki real cap kis frequency par help karna band kar deta hai	Self-resonance $f_{0}$ ; capacitive band vs inductive band	Ex 6
G	Ek word problem: DVFS ek saath kayi cores jagata hai	Words ko $Δ I$ aur $Δ t$ mein translate karo, phir A & B apply karo	Ex 7
H	Exam twist: ek real cap jo drain bhi hota hai aur uski apni $E S L$ bhi hai	Do droops superpose karo — charge term + $E S L d i / d t$ term	Ex 8
I	Reverse/design: droop aur cap diya gaya hai, sabse tezi wala step nikalo jo yeh cover karta hai	Sizing box ko invert karo $Δ t$ ke liye solve karne ke liye	Ex 9

Hum positive aur negative $d i / d t$ (cells B & C), zero case (D), limit (E), ek frequency-domain case (F), aur word/exam/reverse problems (G–I) cover karte hain. Koi cell khaali nahi hai.

Cell A — Ek decoupling capacitor size karo

Worked example Ex 1 (Cell A) — ek current step se sizing

Ek core $Δ I = 30 A$ ka ek step draw karta hai jo $Δ t = 3 ns$ tak rehta hai. Droop budget $Δ V_{ma x} = 60 mV$ hai. Minimum capacitance nikalo.

Forecast: order of magnitude guess karo — nanofarads? microfarads? millifarads?

Cap ko jo charge $Q$ deliver karna hai woh nikalo. Yaad karo $Q$ (charge, coulombs) $= I \cdot t$ , isliye $Q = Δ I Δ t = 30 \times 3 \times 1 0^{- 9} = 9 \times 1 0^{- 8} C = 90 nC$ . Yeh step kyun? Yahan capacitor ka ek hi kaam hai charge dena; charge = current × time.
Allowed sag se divide karo. $C \geq \frac{Q}{Δ V _{ma x}} = \frac{9 \times 1 0 ^{- 8}}{0.06} = 1.5 \times 1 0^{- 6} F = 1.5 μ F$ . Yeh step kyun? $Q = C Δ V$ , isliye ek fixed charge ke liye, bada $C$ matlab chhota voltage drop. Fixed charge ke worst allowed drop par $C$ ke liye solve karo.

Verify: plug back karo — $C Δ V_{ma x} = 1.5 \times 1 0^{- 6} \times 0.06 = 9 \times 1 0^{- 8} C$ = woh 90 nC jo humein chahiye tha. ✓ Units: $\frac{A \cdot s}{V} = \frac{C}{V} = F$ . ✓ Microfarads, jaise MLCC ke liye forecast kiya tha.

Capacitor droop law ke liye sign convention

Cells B & C — $d i / d t$ ka SIGN decide karta hai sag vs overshoot

Yahi woh part hai jo parent note ne assume kar liya tha lekin kabhi draw nahi kiya. Current change ki direction voltage bump ka sign flip kar deti hai. Figure 1 neeche do panels stack karke plot karta hai: top panel current versus time hai (blue-shaded rising edge, pink-shaded falling edge), aur bottom panel resulting rail voltage hai. Shaded bands ko neeche trace karo: rising edge (top, blue) ek sag ke saath line up hoti hai (bottom, blue arrow "DROOP"); falling edge (top, pink) ek spike ke saath line up hoti hai (bottom, pink arrow "OVERSHOOT").

Figure — Voltage droop and decoupling capacitors

Figure 1 — Top: load current ek rising edge (blue band) aur ek falling edge (pink band) ke saath. Bottom: rail voltage apni 1.0 V nominal (yellow dashed) ke around. Rising current → droop; falling current → overshoot. Same edge magnitude, opposite rail direction.

Worked example Ex 3 (Cell C) — falling current, overshoot

Same $L = 150 pH$ . Ab core apna kaam khatam karta hai: current $60 A$ se wapas $10 A$ par $1 ns$ mein girta hai. Rail wobble aur uska sign nikalo.

Forecast: Ex 2 jaisi hi magnitude, lekin rail kis direction mein move karegi?

Slope, sign ke saath. $\frac{d i}{d t} = \frac{10 - 60}{1 \times 1 0 ^{- 9}} = - 5 \times 1 0^{10} A/s$ . Negative — current gir rahi hai. Yeh step kyun? Sign honest rakho; yahi is cell ka poora point hai.
Law apply karo. $V_{L} = 150 \times 1 0^{- 12} \times (- 5 \times 1 0^{10}) = - 7.5 V$ . Yeh step kyun? Same law, negative slope → negative $V_{L}$ , jo chip par rail ke $7.5 V$ upar spring karne ke roop mein dikhta hai (ek overshoot).

Verify: magnitude Ex 2 se same ( $7.5 V$ ), sign opposite. ✓ Figure 1 mein pink falling edge se match karta hai. Lesson: current burst ka ant utna hi khatarnak hai jitna start — decoupling caps overshoot bhi absorb karte hain.

Cell D — the zero/degenerate case ( $d i / d t = 0$ )

Worked example Ex 4 (Cell D) — steady DC, koi change nahi

Ek block $L = 150 pH$ aur $R = 0.5 m Ω$ wale path se constant $I = 40 A$ draw karta hai. Abhi (steady state mein) droop kya hai?

Forecast: kya inductance matter karta hai agar kuch change nahi ho raha?

Inductive term. Current constant hai, isliye $\frac{d i}{d t} = 0$ , deta hai $V_{L} = L \cdot 0 = 0 V$ . Yeh step kyun? Ek inductor sirf change par react karta hai. Ek steady flow usmein se koi voltage develop nahi karta. Yeh degenerate case hai jahan "villain" gayab ho jaata hai — isliye yeh cell IR-only ho jaati hai.
Resistive term bachta hai. $V_{R} = I R = 40 \times 0.5 \times 1 0^{- 3} = 0.02 V = 20 mV$ . Yeh step kyun? Resistance hamesha current ke proportion mein voltage drop karta hai — yeh kabhi nahi sota, DC par bhi.

Verify: total steady droop $= V_{L} + V_{R} = 0 + 20 mV = 20 mV$ . ✓ Sirf resistor contribute karta hai; yeh woh "DC droop" hai jo parent ki table $R$ ko attribute karti hai. Ek cap DC droop fix nahi karta — yeh regulator ka kaam hai.

Cell E — the limit ( $Δ t \to 0$ )

Worked example Ex 5 (Cell E) — transition ko zero tak squeeze karo

Ex 2 ka step lo ( $Δ I = 50 A$ , $L = 150 pH$ ) lekin poocho: $V_{L}$ ka kya hota hai jab transition time $Δ t$ shar karta hai: $1 ns$ , $100 ps$ , $10 ps$ ?

Forecast: kya droop level off hota hai, ya bina bound ke badhta rehta hai?

Droop ko $Δ t$ ke function ke roop mein likho. $V_{L} (Δ t) = L \frac{Δ I}{Δ t} = 150 \times 1 0^{- 12} \times \frac{50}{Δ t}$ . Yeh step kyun? $Δ t$ ko chhodkar sab kuch fix karo taaki hum trend dekh sakein.
Teen points evaluate karo.
- $Δ t = 1 ns$ : $V_{L} = 7.5 V$ .
- $Δ t = 100 ps$ : $V_{L} = 75 V$ .
- $Δ t = 10 ps$ : $V_{L} = 750 V$ . Yeh step kyun? Numbers trend ko undeniable banate hain.
Limit lo. Jab $Δ t \to 0$ , $V_{L} = \frac{L Δ I}{Δ t} \to \infty$ . Yeh step kyun? Ek fixed number ko zero ki taraf jaane wali cheez se divide karne par woh blow up hota hai. Yeh mathematical statement hai "tum ek inductor se instantly current kabhi jump nahi karwa sakte."

Verify: $Δ t$ mein har tenfold decrease $V_{L}$ ko das guna kar deta hai (7.5 → 75 → 750). ✓ Limit wajah hai ki charge ek nearby, low-inductance cap se aana chahiye: chahe edge kitni bhi tez ho, local cap ka $Δ V = Δ I Δ t / C$ actually shrink karta hai jab $Δ t \to 0$ , isliye cap exactly wahin jeetta hai jahan wire fail karti hai.

Cell F — self-resonance aur teen frequency bands

Ab hum time se frequency par switch karte hain. Frequency kyun? Kyunki ek real cap ek pure capacitor nahi hai — usmein series inductance ( $E S L$ , uska apna internal inductance) aur resistance ( $E S R$ , uska apna internal resistance) hai, aur cap help karta hai ya nahi yeh depend karta hai ki disturbance kitni tez (kya frequency) hai. Figure 2 neeche cap ki impedance magnitude $∣ Z ∣$ (vertical axis, ohms) ko frequency $f$ (horizontal axis, Hz) ke against plot karta hai, dono log scales par. Blue dashed line falling capacitive reactance $1/ (ω C)$ hai; pink dashed line rising inductive reactance $ω E S L$ hai; solid white curve real cap hai, jo left par blue follow karta hai, yellow $E S R$ floor par dip karta hai, phir right par pink follow karta hai.

Figure 2 — Ek real capacitor ki impedance vs frequency. $f_{0}$ ke left mein: capacitive (blue), cap kaam karta hai. $f_{0}$ par (yellow line): impedance $E S R$ par bottom out karta hai (yellow dotted floor). $f_{0}$ ke right mein: inductive (pink), cap useless hai. $ω = 2 π f$ angular frequency hai.

Worked example Ex 6 (Cell F) —

$f_{0}$ nikalo aur dono sides check karo Ek cap mein $C = 220 nF$ aur $E S L = 0.8 nH$ , $E S R = 5 m Ω$ hai. Uski self-resonant frequency, aur $f_{0}$ par uski impedance nikalo.

Forecast: tens of MHz? hundreds?

Product compute karo. $E S L \cdot C = 0.8 \times 1 0^{- 9} \times 220 \times 1 0^{- 9} = 1.76 \times 1 0^{- 16} s^{2}$ . Yeh step kyun? $f_{0}$ ko $E S L \cdot C$ ka square root chahiye; pehle product nikalo.
Resonance formula lo (upar derive ki gayi). $f_{0} = \frac{1}{2 π 1.76 \times 1 0 ^{- 16}} = \frac{1}{2 π \times 1.327 \times 1 0 ^{- 8}} \approx 1.20 \times 1 0^{7} Hz = 12.0 MHz$ . Yeh step kyun? Yeh woh frequency hai jahan inductive aur capacitive reactances equal hain aur cancel ho jaate hain.
$f_{0}$ par impedance. Exactly $f_{0}$ par reactances cancel ho jaate hain, sirf $∣ Z ∣ = E S R = 5 m Ω$ bachta hai. Yeh step kyun? Minimum impedance = resistive floor (Figure 2 mein yellow dotted line). $f_{0}$ ke neeche cap help karta hai; uske upar, ek chhota cap add karo jiska $f_{0}$ zyada ho.

Verify: $1.76 \times 1 0^{- 16} = 1.327 \times 1 0^{- 8}$ ; $2 π \times 1.327 \times 1 0^{- 8} = 8.34 \times 1 0^{- 8}$ ; reciprocal $= 1.199 \times 1 0^{7} Hz$ . ✓ ≈ 12 MHz. General $L C$ picture ke liye LC resonance and impedance dekho aur $E S L$ kahan se aata hai ke liye Parasitic inductance and ESL/ESR dekho.

Cell G — ek real-world word problem (DVFS)

Worked example Ex 7 (Cell G) — DVFS ke under cores jagte hain

Ek power-management unit Dynamic voltage and frequency scaling (DVFS) use karke ek saath 8 idle cores jagata hai. Har core on hone par $6 A$ add karta hai, aur gating hardware unhe sab $Δ t = 4 ns$ mein ramp up karta hai. Rail $0.9 V$ hai aur $V_{min} = 0.82 V$ . Nearest bulk cap tak path inductance $L = 120 pH$ hai. Kya die sirf inductive droop par safe hai, aur agar nahi, toh kaun sa cap ise rokta hai?

Forecast: kya 8 cores ek saath $V_{min}$ trip kar denge?

Words ko $Δ I$ mein translate karo. $Δ I = 8 \times 6 = 48 A$ . Yeh step kyun? "8 cores × 6 A" simply total simultaneous demand hai — yeh di-dt and simultaneous switching noise action mein hai.
Inductive droop. $V_{L} = L \frac{Δ I}{Δ t} = 120 \times 1 0^{- 12} \times \frac{48}{4 \times 1 0 ^{- 9}} = 120 \times 1 0^{- 12} \times 1.2 \times 1 0^{10} = 1.44 V$ . Yeh step kyun? Path inductance se change ki rate raw droop set karti hai kisi bhi local cap ke act karne se pehle.
Budget se compare karo. Allowed droop $= 0.9 - 0.82 = 0.08 V = 80 mV$ . Kyunki $1.44 V ≫ 80 mV$ , safe nahi — far cap bahut zyada inductance ke peeche hai. Yeh step kyun? $V_{min}$ ke against go/no-go check.
Local cap size karo jo rail hold kare. $C \geq \frac{Δ I Δ t}{Δ V _{ma x}} = \frac{48 \times 4 \times 1 0 ^{- 9}}{0.08} = \frac{1.92 \times 1 0 ^{- 7}}{0.08} = 2.4 \times 1 0^{- 6} F = 2.4 μ F$ . Yeh step kyun? Ek local, low- $E S L$ cap $Q = Δ I Δ t = 192 nC$ supply karta hai taaki wire ka $L d i / d t$ die par kabhi appear na ho.

Verify: charge $= 48 \times 4 \times 1 0^{- 9} = 1.92 \times 1 0^{- 7} C$ ; $C Δ V = 2.4 \times 1 0^{- 6} \times 0.08 = 1.92 \times 1 0^{- 7} C$ . ✓ Match. Fix $2.4 μ F$ local cap hai, ek bada far wala nahi.

Cell H — exam twist: dono effects superpose karo

Worked example Ex 8 (Cell H) — cap hold up karta hai, lekin uski apni ESL bite karti hai

Ek $1 μ F$ cap ( $E S L = 0.5 nH$ , $E S R = 8 m Ω$ ) ek $Δ I = 20 A$ step $Δ t = 2 ns$ mein supply karta hai. Total droop estimate karo, (a) charge-depletion droop aur (b) cap ki apni $E S L$ ke across extra droop combine karke.

Forecast: kaun sa term dominate karta hai — $C$ term ya $E S L$ term?

Charge-depletion droop (the $C$ term). Magnitude $Δ V_{C} = \frac{Δ I Δ t}{C} = \frac{20 \times 2 \times 1 0 ^{- 9}}{1 0 ^{- 6}} = 4 \times 1 0^{- 2} V = 40 mV$ . Yeh step kyun? Bucket itna khaali hota hai jab woh charge deliver karta hai (upar signed law ke anusaar ek sag).
ESL droop (cap ke andar inductive term). $Δ V_{E S L} = E S L \frac{Δ I}{Δ t} = 0.5 \times 1 0^{- 9} \times \frac{20}{2 \times 1 0 ^{- 9}} = 0.5 \times 1 0^{- 9} \times 1 0^{10} = 5 V$ . Yeh step kyun? Cap ki apni tiny series inductance bhi fast edge ke dauran $L d i / d t$ follow karti hai.
Compare aur combine karo. $Δ V_{E S L} = 5 V ≫ Δ V_{C} = 40 mV$ . Total worst-case magnitude $\approx 5.04 V$ , bilkul $E S L$ se dominate. Yeh step kyun? Twist: ek "accha" cap bhi 2 ns edge par fail karta hai apni $E S L$ ki wajah se — yahi wajah hai ki sabse tez events ke liye hume aur bhi chhote, lower- $E S L$ on-package caps chahiye.

Verify: $Δ V_{C} = 40 mV$ ✓; $Δ V_{E S L} = 5 V$ ✓. $E S L$ term $125 \times$ bada hai. ✓ Lesson: ns-scale spikes ke liye, $E S L$ — $C$ nahi — sab kuch decide karta hai (dekho Parasitic inductance and ESL/ESR).

Cell I — reverse/design problem

Worked example Ex 9 (Cell I) — cap diya gaya hai, kitna tez step woh survive kar sakta hai?

Tumhare paas pehle se ek $0.47 μ F$ cap installed hai. Droop budget $Δ V_{ma x} = 50 mV$ hai aur expected current step $Δ I = 15 A$ hai. Sabse lamba transition $Δ t$ kya hai jo yeh cap sirf charge par cover kar sakta hai?

Forecast: nanoseconds? tens of nanoseconds?

Sizing formula invert karo. $C \geq \frac{Δ I Δ t}{Δ V _{ma x}}$ se, boundary $Δ t$ ke liye solve karo: $Δ t = \frac{C Δ V _{ma x}}{Δ I}$ . Yeh step kyun? Design question flip karta hai ki kaun sa variable unknown hai; algebra hai, koi nayi physics nahi.
Plug in karo. $Δ t = \frac{0.47 \times 1 0 ^{- 6} \times 0.05}{15} = \frac{2.35 \times 1 0 ^{- 8}}{15} = 1.567 \times 1 0^{- 9} s \approx 1.57 ns$ . Yeh step kyun? Known cap, budget, aur step ka direct substitution.

Verify: plug back karo — $\frac{Δ I Δ t}{C} = \frac{15 \times 1.567 \times 1 0 ^{- 9}}{0.47 \times 1 0 ^{- 6}} = \frac{2.35 \times 1 0 ^{- 8}}{4.7 \times 1 0 ^{- 7}} = 0.05 V = 50 mV$ . ✓ Exactly budget. Agar real event 1.57 ns se tez hai toh upstream ek tez (chhota, lower- $E S L$ ) cap add karna hoga.

Recall Main kis cell mein hoon? (compute karne se pehle decide karo)

Current step diya gaya hai aur droop budget hai, $C$ nikalna hai? ::: Cell A — use karo $C \geq Δ I Δ t /Δ V_{ma x}$ .
Current inductance se rise ho raha hai? ::: Cell B — $V_{L} > 0$ , ek droop (sag).
Current gir raha hai? ::: Cell C — $V_{L} < 0$ , ek overshoot (upar spike).
Current constant hai? ::: Cell D — $V_{L} = 0$ , sirf $I R$ bachta hai.
Transition time $\to 0$ ? ::: Cell E — droop $\to \infty$ ; sirf ek local cap isse escape karta hai.
Pucha gaya kis frequency par cap help karna band karta hai? ::: Cell F — $f_{0} = 1/ (2 π E S L C)$ ke upar.

Connections

6.4.09 Voltage droop and decoupling capacitors (Hinglish)
Power Delivery Network (PDN)
Parasitic inductance and ESL/ESR
di-dt and simultaneous switching noise
Clock timing margin and Vmin
Dynamic voltage and frequency scaling (DVFS)
LC resonance and impedance

Worked examples — Voltage droop and decoupling capacitors