6.4.9
Jab ek chip achanak zyada current maangti hai (ek billion transistors ek saath switch karte hain), to power supply use turant deliver nahi kar sakti kyunki chip ko current pahunchaane wali wires mein inductance aur resistance hoti hai. Chip ke power pins par voltage momentarily gir jaati hai — is giraavat ko voltage droop kehte hain. Decoupling capacitors chhoti local "battery buckets" hoti hain jo chip ke bilkul paas rakhi jaati hain aur pehle nanoseconds mein apna stored charge dump kar deti hain, voltage ko tab tak thaami rakhti hain jab tak dheemi supply catch up nahi karti.
Load ki current demand I V Power Delivery Network (PDN) impedance Z P D N Δ I Δ V = − Δ I ⋅ Z P D N V V min galat bits produce karti hai (timing failures).
PDN sirf ek resistor nahi hai. Iske teen parts hain jo teen timescales par matter karte hain:
Element
Symbol
Kis timescale par dominate karta hai
Resistance
R steady state (DC)
Inductance
L fast current changes (d i / d t
Capacitance
C locally charge provide karta hai
Door-baitha voltage regulator ek bade inductance L L change ko resist karta hai — use apni current ramp karne mein time lagta hai. Us time mein charge kaun supply karta hai? Chip ke bilkul paas baitha capacitor, jiske aur load ke beech almost koi inductance nahi, voltage ko thaame rakhne ke liye khud khaalii ho jaata hai.
Step 1 — Capacitor kya store karta hai. Charge Q = C V i C = d t d Q = C d t d V
Step 2 — Poocho ki cap akele supply karte waqt voltage kitna drop hogi.
Current spike ke dauran current Δ I Δ t Δ V = C 1 ∫ i d t ≈ C Δ I ⋅ Δ t Yeh step kyun? Humne i C = C d V / d t C Yehi wajah hai ki capacitors bade hote hain.
Step 3 — Capacitor ko size karo. Ek allowed droop budget Δ V ma x C ≥ Δ V ma x Δ I ⋅ Δ t
Step 4 — Ek capacitor kaafi kyun nahi (frequency picture). Har real cap mein parasitic series inductance (E S L E S R Z c a p ( ω ) = E S R + j ω E S L + j ω C 1
Low ω par: ω C 1 Iske self-resonant frequency f 0 = 2 π E S L ⋅ C 1 = E S R
f 0 ω E S L inductor jaisa dikhne lagta hai aur help karna band kar deta hai.
Yeh kyun matter karta hai: koi ek cap saari frequencies cover nahi kar sakta, isliye hum ek hierarchy use karte hain.
Definition Decoupling hierarchy (har cap ek frequency band cover karta hai)
Bulk caps (100s of µF, board par): slow droop, kHz–MHz.Ceramic MLCCs (µF–nF, package ke paas): MHz–100s MHz.On-die / on-package caps (pF–nF): sabse fast ns-scale spikes.
Chip ke paas = low inductance = fast events handle karta hai. Rule yeh hai: fast events ko physically close stored charge chahiye.
Worked example 1 — Decoupling cap ko size karoEk core Δ I = 20 A Δ t = 2 ns Δ V ma x = 50 mV C C ≥ Δ V ma x Δ I Δ t = 0.05 20 ⋅ 2 × 1 0 − 9 = 8 × 1 0 − 7 F = 0.8 μ F Yeh step kyun? Humne Step 3 ka box use kiya — cap ko Q = Δ I Δ t = 40 nC
Worked example 2 — Wire ka inductive droopWire inductance L = 200 pH 50 A 1 ns V L = L d t d i = 200 × 1 0 − 12 ⋅ 1 × 1 0 − 9 50 = 10 V Yeh step kyun? Pure L d i / d t pehle ZAROOR baithhni chahiye, baad mein nahi.
Worked example 3 — Self-resonant frequencyC = 100 nF E S L = 1 nH f 0 f 0 = 2 π E S L ⋅ C 1 = 2 π 1 0 − 9 ⋅ 1 0 − 7 1 = 2 π 1 0 − 16 1 ≈ 15.9 MHz Yeh step kyun? 16 MHz ke upar yeh cap inductive hai → wahan useless → to tum chhote caps add karte ho jinki f 0
Common mistake "Bas ek bada capacitor laga do."Sahi kyun lagta hai: formula Δ V = Δ I Δ t / C C C Fix: bade caps mein high E S L f 0 low hoti hai — woh GHz par inductive hote hain aur fast spikes ke liye useless hote hain. Tumhe ek giant cap nahi, balki kaafi caps ki band-covered hierarchy chahiye.
Common mistake "Droop current kitna hai us par depend karta hai, kitni jaldi nahi."Sahi kyun lagta hai: intuitively zyada current = bada sag, aur DC (I R I Fix: dangerous transient droop L d i / d t change ki rate par depend karta hai. Ek chhota lekin sudden current step ek bade steady current se zyada takleef deta hai.
Common mistake "Decoupling cap ko board par kahin bhi rakh do."Sahi kyun lagta hai: electrically same net hai.
Fix: distance cap aur die ke beech trace inductance add karta hai. Loop inductance hi cap ko slow banata hai; ise power pins ke jitna ho sake utna paas rakho.
Recall Feynman: explain to a 12-year-oldSocho door ek water tap hai aur ek baccha achanak bahut pyaasa ho jaata hai. Agar woh jaldi jaldi peene lagey, to paani lambi pipe mein turant nahi aayega — cup par pressure drop ho jaayega. Isliye hum bacche ke bilkul paas ek cup paani rakhte hain (capacitor). Jab woh ghoontp leta hai, pehle cup khaali hota hai aur pressure thaama rehta hai jab tak door ka tap catch up nahi karta. Chhote cups turant react karte hain lekin jaldi khaali ho jaate hain; bade tanks dheeme hain lekin zyada rakhte hain — isliye hum alag-alag distances par kai sizes rakhte hain.
"Close caps chase fast currents."
Aur droop ki wajah ke liye: "Yeh kitna zyada hai nahi, kitna fast hai" (L d i / d t
Current magnitude nahi, kaun si quantity worst droop cause karti hai? ⟶ d i / d t
Self-resonant frequency ke upar ek capacitor ___ ki tarah behave karta hai ⟶ inductor
Caps ki hierarchy kyun? ⟶ har size ek alag frequency band cover karta hai
Voltage droop physically kya cause karta hai? PDN impedance (R L C Δ V = − Δ I ⋅ Z P D N
Inductive droop ka formula? V L = L d i / d t
Current step ke liye decoupling cap size karne ka formula? C ≥ Δ I ⋅ Δ t /Δ V ma x
Large steady current se d i / d t Inductors current change ko resist karte hain, isliye fast slews chhote current par bhi bade L d i / d t
Capacitor ki self-resonant frequency kya hoti hai? f 0 = 1/ ( 2 π E S L ⋅ C ) ; iske neeche capacitive hota hai, upar inductive (useless) hota hai.
Decoupling caps ki hierarchy kyun use karte hain? Har cap size ek alag frequency band cover karta hai; koi ek cap saari frequencies par low impedance nahi rakh sakta.
Decoupling caps ko die ke paas kyun rakhte hain? Cap aur load ke beech loop inductance minimize karne ke liye taaki charge fast deliver ho sake.
Agar droop V ko V min Transistors timing fail karte hain → galat bits / logic errors.
Sabse fast (ns) spikes kaun sa cap handle karta hai? On-die / on-package caps (sabse chhote, sabse paas, lowest inductance).
Resonance par capacitor ki impedance kya hoti hai? Iska minimum, E S R
Fast current change dI/dt
Wrong bits timing failure
Sizing C >= dI dt / dVmax
Multiple caps across frequencies
