Power, Thermal & Reliability

Question 1 (12)

(a) Dynamic power derivation (5)

• Each low→high transition charges $C$ to $V$; energy drawn from supply $= CV^2$, of which $\tfrac12 CV^2$ is stored on the capacitor and $\tfrac12 CV^2$ dissipated in the pull-up. On high→low, the stored $\tfrac12 CV^2$ dissipates in the pull-down. So one full switching cycle dissipates $CV^2$. (2 marks — energy argument)
• Transitions happen at rate $\alpha f$ where $f$ is the clock frequency and $\alpha$ is the activity factor (probability/fraction of clocks with a switching transition, $0\le\alpha\le1$). (1)
• Therefore $P_{dyn} = \alpha C V^2 f$ (1 for equation) — symbols: $C$ effective switched capacitance, $V$ supply voltage, $f$ clock frequency, $\alpha$ activity factor. (1 for definitions)

(b) Static power (4)

• $P_{static} = V \cdot I_{leak}$ (or $V I_{sub} + \dots$). (1)
• Two dominant mechanisms: subthreshold leakage (current through "off" transistors, exponential in $-V_{th}$) and gate-oxide tunnelling leakage (through thin dielectric). (2)
• As nodes shrank, $V_{th}$ was lowered (to keep switching speed as $V$ dropped) and oxides thinned → subthreshold and tunnelling both rose exponentially, so static became a large fraction of total power. (1)

(c) Numeric (3) $P_{dyn} = 0.15 \times 2\times10^{-9} \times (1.0)^2 \times 2.5\times10^9 = 0.75\text{ W}$ (3 marks: setup + arithmetic + units)

Question 2 (12)

(a) Explain-out-loud (4)

• $P_{dyn}=\alpha C V^2 f$ so power ∝ $V^2 f$ directly. (1)
• Energy for a fixed workload = power × time; time to finish the workload ∝ $1/f$ (higher clock finishes sooner). (2)
• So $E = P\cdot t \propto (V^2 f)\cdot(1/f) = V^2$ — the $f$ cancels. Lowering $f$ saves power but not energy per task; lowering $V$ is what saves energy. (1)

(b) Numeric (5) Ratio: $C,\alpha$ constant, so $P_2 = P_1 \frac{V_2^2 f_2}{V_1^2 f_1} = 40\cdot\frac{0.9^2\cdot 2.0}{1.1^2\cdot 3.0}$ (2 setup) $= 40 \cdot \frac{0.81\times2.0}{1.21\times3.0} = 40\cdot\frac{1.62}{3.63} = 40\times0.4463 \approx 17.85\text{ W}$ (3 for arithmetic; accept 17.8–17.9 W)

(c) Physical limit (3)

• $V$ cannot go below (a small margin above) the transistor threshold voltage $V_{th}$; near/subthreshold operation makes gates too slow and noise-sensitive, and leakage relative to dynamic grows. (2) Consequence: DVFS has a minimum voltage floor, so energy savings from voltage scaling saturate. (1)

Question 3 (10)

(a) TDP (3) — TDP is the maximum sustained power the cooling system must be designed to dissipate under a realistic sustained workload, i.e. the thermal design target. (2) It is not peak instantaneous draw: chips can briefly exceed TDP (turbo/boost) using thermal mass, and worst-case power viruses can exceed it. (1)

(b) Numeric (4) Total $\theta_{JA} = 0.2+0.1+0.4 = 0.7\text{ °C/W}$. (1) $T_J = T_A + P\cdot\theta_{JA} = 35 + 95\times0.7 = 35 + 66.5 = 101.5\text{ °C}$ (3)

(c) Throttling (3) — $T_J = 101.5\text{ °C} > 100\text{ °C}$ limit, so the chip does need throttling. (1) Throttling reduces $f$ (and $V$ via DVFS) to cut power until $T_J$ falls below the limit, trading performance for thermal safety. (2)

Question 4 (10)

(a) Contrast (6) — 2 marks each row:

(b) Dark silicon (4) — With Dennard scaling dead ($V$ no longer scales with feature size), power density stays high, so at each node you can fit more transistors than you can power/cool at once. (2) The fraction that must stay off is "dark silicon." Power gating helps by turning off idle regions, but the total power/thermal budget is still fixed, so you fundamentally cannot run all transistors at full speed simultaneously — gating manages, not removes, the constraint. (2)

Question 5 (10)

(a) Black's equation (4) $MTTF = \frac{A}{J^n}\,\exp\!\left(\frac{E_a}{kT}\right)$ (2) — $A$ material constant, $J$ current density, $n$ exponent (~2), $E_a$ activation energy, $k$ Boltzmann, $T$ absolute temperature. Higher $J$ → more momentum transfer to metal ions → faster void/hillock formation → shorter life (∝ $J^{-n}$). Higher $T$ → exponentially faster diffusion → shorter life. (2)

(b) Voltage droop + decaps (6)

• On a sudden current surge, the current through the parasitic package/board inductance $L$ and resistance $R$ causes a supply drop $\Delta V \approx IR + L\,\tfrac{di}{dt}$. (2) The $L\,di/dt$ term dominates for fast transients — the PDN cannot deliver charge instantaneously, so local $V_{dd}$ droops. (1)
• Decoupling capacitors act as local charge reservoirs supplying the transient demand before the main PDN responds, flattening $\Delta V$. (2)
• Placed in a hierarchy: on-die (small, fastest, highest frequency transients) → package → board/bulk caps (large, slow). (1)

Question 6 (6)

• Performance per watt = useful work (ops, IPC, throughput) delivered per unit power (or energy). (2)
• Governing metric because: mobile is battery/thermally limited (fixed energy budget), and datacenter total cost / density is dominated by power delivery and cooling; raw performance is meaningless if you cannot power or cool it. (2)
• Example: using many simpler, lower-clock (in-order or narrow) cores instead of one wide high-clock core — raises throughput-per-watt but each thread is slower. (Accept: lowering clock via DVFS, wider SIMD at low frequency, big.LITTLE small cores.) (2)

[
  {"claim":"Q1c dynamic power = 0.75 W","code":"P=0.15*2e-9*(1.0**2)*2.5e9; result = abs(P-0.75)<1e-9"},
  {"claim":"Q2b DVFS scaled power approx 17.85 W","code":"P2=40*(0.9**2*2.0)/(1.1**2*3.0); result = abs(P2-17.85)<0.1"},
  {"claim":"Q3b junction temperature = 101.5 C","code":"theta=0.2+0.1+0.4; Tj=35+95*theta; result = abs(Tj-101.5)<1e-9"},
  {"claim":"Q3 chip exceeds 100 C limit so throttling needed","code":"theta=0.2+0.1+0.4; Tj=35+95*theta; result = bool(Tj>100)"}
]