Level 1 — RecognitionPower, Thermal & Reliability

Power, Thermal & Reliability

⏱ 20 minutes30 marksprintable — key stays hidden on paper

Chapter: 6.4 Power, Thermal & Reliability Level: 1 — Recognition (MCQ, Matching, True/False with justification) Time Limit: 20 minutes Total Marks: 30

Section A — Multiple Choice (1 mark each) — 10 marks

Q1. The dynamic power of a CMOS circuit is best approximated by which expression? ( $C$ = capacitance, $V$ = voltage, $f$ = frequency, $\alpha$ = activity factor)

A. $P = \alpha C V f$ B. $P = \alpha C V^2 f$ C. $P = C V^2 / f$ D. $P = \alpha C^2 V f$

Q2. Static (leakage) power consumption is primarily caused by:

A. Charging and discharging of load capacitance B. Clock signal toggling C. Subthreshold and gate leakage currents while transistors are idle D. Switching activity of logic gates

Q3. In DVFS, reducing frequency alone (without lowering voltage) changes dynamic power:

A. Quadratically B. Linearly C. Cubically D. Not at all

Q4. Thermal Design Power (TDP) specifies:

A. The absolute maximum instantaneous power a chip can ever draw B. The maximum sustained heat the cooling system must be designed to dissipate C. The idle power of the processor D. The static leakage power only

Q5. Clock gating primarily reduces:

A. Static leakage power B. Dynamic power by stopping the clock to idle blocks C. The chip's silicon area D. Electromigration

Q6. Power gating differs from clock gating because power gating:

A. Only stops the clock signal B. Cuts off the supply voltage to a block, eliminating leakage too C. Increases voltage to idle blocks D. Is a purely software technique

Q7. The "dark silicon" problem refers to:

A. Silicon defects visible under a microscope B. The fraction of a chip that must stay powered off at a given time due to power/thermal limits C. Transistors that never switch D. Silicon coated with a dark thermal paste

Q8. Electromigration is a reliability failure mechanism caused by:

A. Excessive clock frequency B. Momentum transfer from electrons displacing metal atoms in interconnects C. Software bugs D. Overvoltage on the gate oxide

Q9. Decoupling capacitors are placed near circuits mainly to:

A. Increase the clock frequency B. Supply transient current and reduce voltage droop C. Cool the chip D. Reduce silicon area

Q10. "Performance per watt" is a metric that improves when:

A. Power increases faster than performance B. Performance increases while power stays the same or drops C. The clock is disabled entirely D. TDP is exceeded

Section B — Matching (1 mark each) — 6 marks

Q11–Q16. Match each term (left) to its correct description (right). Write the letter.

#	Term		Description
11	Thermal throttling	A	Metal ion migration degrading wires over time
12	Heat sink / heat pipe	B	Reducing clock/voltage automatically when temperature limit is hit
13	Electromigration	C	Passive/active cooling solution that conducts heat away from the die
14	Activity factor ( $\alpha$ )	D	Powered-off portions of a many-core chip under a power budget
15	Dark silicon	E	Fraction of gates that switch per clock cycle
16	Decoupling capacitor	F	Local charge reservoir smoothing supply voltage transients

Section C — True/False WITH Justification (2 marks each: 1 mark T/F, 1 mark justification) — 14 marks

Q17. Lowering supply voltage in DVFS reduces dynamic power more effectively than lowering frequency alone. True or False? Justify.

Q18. TDP equals the peak instantaneous power a CPU can momentarily draw. True or False? Justify.

Q19. Power gating can reduce static leakage power to near zero in an idle block, whereas clock gating cannot. True or False? Justify.

Q20. As transistors shrink, static/leakage power has become negligible compared with dynamic power. True or False? Justify.

Q21. Voltage droop occurs when a sudden increase in current demand causes a temporary drop in supply voltage. True or False? Justify.

Q22. Thermal throttling improves peak performance during heavy sustained workloads. True or False? Justify.

Q23. A chip running at half the clock frequency but the same voltage uses one-quarter of its dynamic power. True or False? Justify.

End of Paper

Answer keyMark scheme & solutions

Section A — MCQ (1 mark each)

Q1 — B. $P_{dyn}=\alpha C V^2 f$ . The $V^2$ term comes from energy $\tfrac12 CV^2$ per switching event, times activity and frequency. (1)

Q2 — C. Static power is leakage (subthreshold + gate) that flows even when no switching occurs. (1)

Q3 — B. With $V$ fixed, $P_{dyn}\propto f$ , i.e., linear in frequency. (1)

Q4 — B. TDP is the sustained thermal power the cooling solution must handle, not a hard power cap. (1)

Q5 — B. Clock gating stops the clock to idle blocks, cutting dynamic (switching) power; leakage remains. (1)

Q6 — B. Power gating removes the supply rail from a block, eliminating both dynamic and static power. (1)

Q7 — B. Dark silicon = fraction of the chip that must remain unpowered simultaneously because the full chip can't be powered within thermal/power limits. (1)

Q8 — B. Electromigration: electron momentum transfer displaces metal atoms, forming voids/hillocks in interconnects. (1)

Q9 — B. Decoupling caps deliver transient current locally, minimizing droop ( $V=L\,di/dt$ effects). (1)

Q10 — B. Perf/watt rises when performance grows without a proportional power increase. (1)

Section B — Matching (1 mark each)

Q	Answer
11	B — throttling = reduce clock/voltage on temperature limit
12	C — heat sink/pipe conducts heat away
13	A — electromigration = ion migration degrading wires
14	E — activity factor = fraction of gates switching
15	D — dark silicon = powered-off chip portions
16	F — decoupling cap = local charge reservoir

(1 mark each, 6 total)

Section C — True/False with Justification (2 marks each)

Q17 — TRUE. (1) Justification: dynamic power scales as $V^2 f$ , so voltage enters quadratically while frequency is linear; lowering $V$ gives a larger power reduction per unit change. (Often reducing $V$ requires reducing $f$ too, compounding savings.) (1)

Q18 — FALSE. (1) Justification: TDP is the maximum sustained heat the cooling must dissipate; instantaneous/peak power can briefly exceed TDP (e.g., turbo bursts). (1)

Q19 — TRUE. (1) Justification: power gating disconnects the supply voltage, so leakage current ≈ 0; clock gating only stops switching, leaving the block powered and still leaking. (1)

Q20 — FALSE. (1) Justification: at small nodes leakage rose sharply (thinner oxides, lower thresholds), making static power a significant—sometimes dominant—portion of total power. (1)

Q21 — TRUE. (1) Justification: a sudden $di/dt$ current surge across parasitic inductance/resistance causes a temporary supply-voltage dip (droop); decoupling caps mitigate it. (1)

Q22 — FALSE. (1) Justification: throttling lowers clock/voltage to protect the chip, so it reduces performance under heat; it protects reliability, not boosts peak performance. (1)

Q23 — TRUE. (1) Justification: $P_{dyn}\propto V^2 f$ , but the claim keeps $V$ fixed—wait: check. With $V$ fixed and $f$ halved, $P\propto f$ gives half, not quarter. → FALSE. (1)

Correction (authoritative): Q23 is FALSE. With voltage unchanged, halving frequency halves dynamic power (linear in $f$ ). One-quarter would require also halving voltage ( $(\tfrac12)^2\cdot\tfrac12=\tfrac18$ , or $(\tfrac12)^2$ from voltage alone). Award marks: TRUE→0/2; FALSE with correct linear-frequency reasoning→2/2.

[
  {"claim":"Dynamic power scales as V^2*f (Q1)","code":"C,V,f,a=symbols('C V f a',positive=True); Pdyn=a*C*V**2*f; result = (diff(Pdyn,f)==a*C*V**2) and (simplify(Pdyn/f - a*C*V**2)==0)"},
  {"claim":"Halving f at fixed V halves dynamic power, not quarters it (Q23 FALSE)","code":"C,V,f,a=symbols('C V f a',positive=True); P=a*C*V**2*f; Phalf=P.subs(f,f/2); ratio=simplify(Phalf/P); result = (ratio==Rational(1,2)) and (ratio!=Rational(1,4))"},
  {"claim":"Reducing V quadratically beats reducing f linearly for same fractional cut (Q17)","code":"C,f,a=symbols('C f a',positive=True); V=symbols('V',positive=True); Pfull=a*C*V**2*f; Pvolt=a*C*(V/2)**2*f; Pfreq=a*C*V**2*(f/2); result = simplify(Pvolt/Pfull)==Rational(1,4) and simplify(Pfreq/Pfull)==Rational(1,2) and (Rational(1,4) < Rational(1,2))"},
  {"claim":"Halving both V and f gives 1/8 dynamic power (supports Q23 note)","code":"C,V,f,a=symbols('C V f a',positive=True); P=a*C*V**2*f; Pboth=P.subs({V:V/2,f:f/2}); result = simplify(Pboth/P)==Rational(1,8)"}
]