Scan chains and BIST — Hardware notes

WHY do we need scan and BIST?

WHAT goes wrong without DfT: sequential logic hides FFs behind many clock cycles of combinational logic, so reaching a specific internal state may need thousands of input vectors — the test-generation problem becomes exponential.

HOW we fix it: convert the hard sequential test problem into an easy combinational one by making all FFs directly loadable/readable.

Scan Chains

Building a scan flip-flop (derivation from scratch)

Start with a normal D flip-flop capturing logic data $D$ . We want a second mode where instead of $D$ it captures the previous FF in the chain, $SI$ (scan-in). Insert a 2:1 MUX before the D input, controlled by Scan Enable (SE):

D_{\text{ff}} = \overline{SE}\cdot D \;+\; SE\cdot SI

Why this step? When $SE=0$ (normal/functional mode) the FF behaves exactly as before ( $D_{\text{ff}}=D$ ). When $SE=1$ (shift mode) the FF takes $SI$ from its neighbour, so all FFs form a shift register. One control signal switches the whole chip between "compute" and "shift."

The three phases of a scan test

\underbrace{\text{Shift-In}}_{SE=1,\; N \text{ clocks}} \;\to\; \underbrace{\text{Capture}}_{SE=0,\; 1 \text{ clock}} \;\to\; \underbrace{\text{Shift-Out}}_{SE=1,\; N \text{ clocks}}

Shift-In: $SE=1$ ; clock $N$ times to load an $N$ -bit test pattern into the $N$ FFs.
Capture: $SE=0$ ; clock once so the combinational logic result is captured back into the FFs.
Shift-Out: $SE=1$ ; shift the captured response out (usually overlapped with shifting in the next pattern).

Built-In Self-Test (BIST)

Why an LFSR gives long sequences (derivation)

An $n$ -bit LFSR with XOR feedback taps evolves as $s_{t+1}=A\,s_t$ over $GF(2)$ . If the feedback polynomial is primitive of degree $n$ , the state cycles through all non-zero states:

\text{Period} = 2^{n}-1

Why $-1$ ? The all-zeros state is a fixed point ( $A\cdot 0 = 0$ ), so it is excluded from the cycle. Why primitive? A primitive polynomial's roots have maximal multiplicative order, guaranteeing every non-zero state is visited exactly once (a maximal-length or m-sequence).

The signature idea

The MISR maps the (very long) response bit-stream to an $n$ -bit signature. Compare it to the pre-computed golden signature:

Match → chip PASS. Mismatch → chip FAIL.

Common Mistakes (Steel-manned)

Flashcards

What two properties must a node have to be testable?

Controllability and observability.

What logic is inserted in front of a scan flip-flop?

A 2:1 MUX selected by Scan Enable (SE), choosing between functional D and scan-in SI.

Write the scan FF input equation.

D_{ff}=\overline{SE}\cdot D + SE\cdot SI

Name the three phases of a scan test.

Shift-in (SE=1), Capture (SE=0, 1 clock), Shift-out (SE=1).

Why is Capture only one clock cycle?

To latch the combinational logic response back into the same FFs before shifting out.

Why split one long scan chain into M parallel chains?

To reduce shift length to N/M, cutting test time ~M×.

What does an LFSR generate in BIST?

A pseudo-random maximal-length test-pattern sequence (PRPG).

What is the period of a maximal LFSR of n bits and why not 2^n?

2^n-1

; the all-zeros state is a fixed point and excluded.

What does a MISR do?

Compacts many response bits into one n-bit signature for comparison with the golden signature.

What is aliasing and its probability?

A faulty response producing the golden signature;

P\approx 2^{-n}

Why must the LFSR polynomial be primitive?

Only then does it visit all

2^n-1

non-zero states (maximal length).

Why does SE timing matter during capture?

SE must be 0 during capture; else the FF grabs the neighbour, invalidating the test.

Recall Feynman: explain to a 12-year-old

Imagine a huge factory with thousands of tiny rooms, but only a few doors to the whole building. You can't check every room by walking in. So we connect all the rooms with a secret conveyor belt. To test, you put a note into each room along the belt, let the machines do one step of work, then run the belt again to read all the notes coming out. That's a scan chain. BIST is even lazier: we build a little robot inside that writes random notes, collects the answers, squishes them into one number, and just tells you "everything's fine" or "something's broken."

Connections

Flip-flops and Latches — the storage element scan modifies.
Fault Models (Stuck-at, Bridging) — what scan/BIST actually detect.
ATPG (Automatic Test Pattern Generation) — produces the patterns shifted in.
Linear Feedback Shift Registers — mathematics of LFSR/MISR over $GF(2)$ .
JTAG Boundary Scan — related standard for board-level access.
Design for Testability — the umbrella methodology.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, ek modern chip ke andar millions of flip-flops hote hain, lekin package pe pins sirf kuch sau. Toh andar ke har FF tak pahunchna impossible ho jata hai — na hum use set kar paate (controllability), na read kar paate (observability). Iska smart solution hai scan chain: har normal flip-flop ke aage ek chota 2:1 MUX laga do, jise Scan Enable (SE) control karta hai. SE=1 pe saare FFs ek lambi shift register ban jaate hain (beads on a string jaisa), aur SE=0 pe wo normal compute mode me kaam karte hain. Test ke waqt hum pattern shift-in karte hain, phir ek clock de kar logic ka result capture karte hain, phir shift-out kar ke answer bahar nikaalte hain.

Formula yaad rakho: $D_{ff}=\overline{SE}\cdot D + SE\cdot SI$ . Jab SE=0 to functional data $D$ , jab SE=1 to padosi FF ka $SI$ . Test time approx $(P+1)N$ clocks hota hai, isliye ek lambi chain ko $M$ parallel chains me tod dete hain — speed $M$ guna badh jaati hai.

Ab BIST ka idea aur mast hai: bahar wala mehenga tester (ATE) hata do, chip khud ko test kare. Andar ek chota LFSR random patterns banata hai (PRPG), aur ek MISR saare responses ko ek chhoti si signature me dabaa deta hai. Us signature ko golden value se compare karo — match hua to PASS, warna FAIL. Yaad rakhna: LFSR ka period $2^n-1$ hota hai ( $2^n$ nahi!), kyunki all-zero state phas jaata hai. Aur signature compaction lossy hai, isliye aliasing ka chance $\approx 2^{-n}$ — bade $n$ (jaise 32-bit) se ye almost zero ho jaata hai. Isliye scan aur BIST milke chip testing ko cheap, fast aur reliable bana dete hain.

Test yourself — VLSI Design

Connections