VLSI Design

Question 1

(a) Dynamic power: $P_{dyn}=\alpha C V_{dd}^2 f = 0.15 \times 15\text{nF} \times (1.0)^2 \times 2\text{GHz}$ $= 0.15 \times 15\times10^{-9} \times 1 \times 2\times10^{9} = 4.5\text{ W}$. (2) Static: $P_{stat}=V_{dd}\,I_{leak}=1.0\times1.2=1.2\text{ W}$. (1) Total $=5.7\text{ W}$. (1)

(b) Ideal Dennard: dimensions $\to 1/k$, $V_{dd}\to V_{dd}/k$, $C\to C/k$, $f\to k\,f$, area $\to 1/k^2$. (1)

• New $V_{dd}=1.0/2=0.5\text{ V}$ (1)
• New $C=15/2=7.5\text{ nF}$ (per equivalent block); $f=2\times2=4\text{ GHz}$ (1)
• New dynamic power $P'=\alpha (C/k)(V/k)^2(kf)=\alpha C V^2 f \cdot \tfrac{1}{k^2}=P_{dyn}/4=1.125\text{ W}$. (1)
• Area scales by $1/k^2=1/4$, so power density $=P'/A' = (P/4)/(A/4)=P/A$ → constant. (1)

(c) Lowering $V_{dd}$ requires lowering $V_{th}$ to preserve drive; but subthreshold leakage $I_{leak}\propto e^{-V_{th}/(nkT/q)}$ rises exponentially as $V_{th}$ falls. So $V_{dd}$ could not keep scaling $\propto 1/k$ without leakage exploding. (2) Consequently the ideal $P/4$ result of (b) is not achievable; static power dominates and power density rises → "power wall." (1)

Question 2

(a) Setup: $t_{cq}+t_{logic}+t_{su}\le T+t_{skew}$. (1.5) Hold: $t_{cq}+t_{logic}\ge t_{h}+t_{skew}$. (1.5)

(b) Setup → $t_{skew}\ge t_{cq}+t_{logic}+t_{su}-T = 90+520+60-800 = -130\text{ ps}$. So $t_{skew,min}=-130\text{ ps}$. (2) Hold → $t_{skew}\le t_{cq}+t_{logic}-t_{h} = 90+520-40 = 570\text{ ps}$. So $t_{skew,max}=570\text{ ps}$. (2) Valid range: $-130\text{ ps}\le t_{skew}\le 570\text{ ps}$. (1)

(c) $+150\text{ ps}$ lies in $[-130,570]$ → both setup and hold met. (2) Useful skew: intentionally delaying the capture clock borrows time for a critical setup path (relaxes setup, at the cost of hold margin on downstream paths), improving max frequency without changing logic. (2)

Question 3

(a) Lumped far-end: $V_{drop}=IR=0.8\times0.5=0.4\text{ V}$. (2) Load voltage $=1.0-0.4=0.6\text{ V}$. (1)

(b) Distributed uniform load: consider current $I(x)$ decreasing linearly from $I$ at source to 0 at the end. Drop $=\int_0^L I(x)\,r\,dx$ where $r=R/L$. With $I(x)=I(1-x/L)$: $V_{drop}=\int_0^L I(1-x/L)\frac{R}{L}dx = \frac{IR}{L}\big[x-\frac{x^2}{2L}\big]_0^L=\frac{IR}{L}\cdot\frac{L}{2}=\tfrac12 IR$. (3) $=0.5\times0.4=0.2\text{ V}$. (1) Physically: current near the far end traverses less resistance (only the near portion carries the full current), so average path resistance is halved. (1)

(c) Distributed load voltage $=1.0-0.2=0.8\text{ V} < 0.9\text{ V}$ → constraint NOT met. (2) Techniques (any two): widen power straps / add more metal layers; use a denser power mesh; add more supply pins/bumps (double-sided feed); insert decoupling capacitors; place high-current blocks near supply. (2)

Question 4

(a) Single chain length = 24,000 bits. Shift time $=24000/(50\times10^6)=4.8\times10^{-4}\text{ s}=480\ \mu s$. (3)

(b) 8 balanced chains → longest chain $=24000/8=3000$ bits. Time $=3000/50\text{MHz}=60\ \mu s$. (2) Speedup $=480/60=8\times$. (1) Trade-off: 8× more scan I/O pins (or more test channels/ATE resources), extra routing congestion. (1)

(c) Per-vector shift $=3000$ cycles; capture $=1$ cycle. With overlap of shift-out/shift-in, effective cost per vector after pipeline fill $\approx 3000+1=3001$ cycles; plus one final shift-out (3000) for the last vector. Cycles $\approx 1200\times3001 + 3000 = 3,601,200+3000=3,604,200$. (3) Time $=3.6042\times10^{6}/50\times10^{6}=0.0721\text{ s}\approx 72.1\text{ ms}$. (2) (Accept ~72 ms; simple estimate $1200\times3001/50\text{MHz}=72.0\text{ ms}$ also full marks.)

Question 5

(a) Capacitive divider: $V_{noise}=\Delta V\cdot\dfrac{C_c}{C_c+C_g}=1.0\times\dfrac{8}{8+24}=1.0\times\dfrac{8}{32}=0.25\text{ V}$. (3) Layout fix (any): increase spacing between nets; insert grounded shield line; reduce parallel run length; route on orthogonal layers. (2)

(b) DRC checks the layout geometry obeys the foundry's manufacturability rules (spacing, width, enclosure, density) — purely physical. (1) LVS verifies the extracted netlist from layout matches the schematic/intended netlist (connectivity + device sizes/types). (1) Example DRC misses but LVS catches: a wire that is geometrically legal but connects the wrong two nets (a short between nets, or a missing/swapped connection) — spacing rules pass but topology is wrong. (2)

(c) Lumped delay $=0.69RC=0.69\times20\times50\times10^{-15}=6.9\times10^{-13}\text{ s}=0.69\text{ ps}$. (2) Distributed-RC delay is lower (~$0.38RC$) because resistance and capacitance are interspersed, so the full $R$ does not charge the full $C$; the lumped model overestimates. (1)

[
  {"claim":"Q1a dynamic and total power", "code":"alpha=Rational(15,100); C=15e-9; V=1.0; f=2e9; Pdyn=alpha*C*V**2*f; Pstat=1.0*1.2; result = (abs(float(Pdyn)-4.5)<1e-6) and (abs(float(Pdyn)+Pstat-5.7)<1e-6)"},
  {"claim":"Q1b scaled dynamic power is 1.125W (P/4)", "code":"k=2; Pdyn=4.5; Pnew=Pdyn/k**2; result = abs(Pnew-1.125)<1e-9"},
  {"claim":"Q2b skew range [-130,570] ps", "code":"tcq=90; tl=520; tsu=60; th=40; T=800; smin=tcq+tl+tsu-T; smax=tcq+tl-th; result = (smin==-130) and (smax==570)"},
  {"claim":"Q3b distributed IR drop = 0.2V", "code":"x=symbols('x'); I=0.8; R=0.5; L=1; expr=I*(1-x/L)*(R/L); drop=integrate(expr,(x,0,L)); result = abs(float(drop)-0.2)<1e-9"},
  {"claim":"Q4 single vs 8-chain shift times and speedup", "code":"N=24000; f=50e6; t1=N/f; t8=(N/8)/f; result = (abs(t1-4.8e-4)<1e-12) and (abs(t8-6e-5)<1e-12) and (abs(t1/t8-8)<1e-9)"},
  {"claim":"Q5a crosstalk noise = 0.25V", "code":"Cc=8; Cg=24; dV=1.0; Vn=dV*Cc/(Cc+Cg); result = abs(Vn-0.25)<1e-9"}
]