Scan chains and BIST — Hinglish notes

4.2.14 · Hardware › VLSI Design

Scan aur BIST ki zaroorat kyun hai?

Bina DfT ke kya gadbad hoti hai: sequential logic FFs ko combinational logic ke kai clock cycles ke peeche chhupaati hai, isliye ek specific internal state tak pahunchne ke liye hazaron input vectors chahiye ho sakte hain — test-generation problem exponential ho jaati hai.

Hum isko kaise fix karte hain: mushkil sequential test problem ko ek aasaan combinational problem mein convert karo by making all FFs directly loadable/readable.

Scan Chains

Scan flip-flop banana (scratch se derivation)

Ek normal D flip-flop se shuru karo jo logic data $D$ capture karta hai. Hum ek second mode chahte hain jahan $D$ ki jagah ye chain mein pichle FF, yaani $S I$ (scan-in) ko capture kare. D input ke pehle ek 2:1 MUX daalo, jise Scan Enable (SE) control karta hai:

D_{ff} = \overline{S E} \cdot D + S E \cdot S I

Ye step kyun? Jab $S E = 0$ (normal/functional mode) hota hai to FF bilkul pehle ki tarah kaam karta hai ( $D_{ff} = D$ ). Jab $S E = 1$ (shift mode) hota hai to FF apne neighbour se $S I$ leta hai, isliye saare FFs ek shift register bana lete hain. Ek control signal poori chip ko "compute" aur "shift" ke beech switch karta hai.

Scan test ke teen phases

S E = 1, N clocks Shift-In \to S E = 0, 1 clock Capture \to S E = 1, N clocks Shift-Out

Shift-In: $S E = 1$ ; $N$ FFs mein $N$ -bit test pattern load karne ke liye $N$ baar clock karo.
Capture: $S E = 0$ ; ek baar clock karo taaki combinational logic ka result wapas FFs mein capture ho jaye.
Shift-Out: $S E = 1$ ; captured response ko shift out karo (aksar agla pattern shift-in karte waqt overlap hota hai).

Built-In Self-Test (BIST)

LFSR long sequences kyun deta hai (derivation)

$n$ -bit LFSR with XOR feedback taps $GF (2)$ par $s_{t + 1} = A s_{t}$ ke roop mein evolve karta hai. Agar feedback polynomial degree $n$ ka primitive hai, to state saare non-zero states se cycle karta hai:

Period = 2^{n} - 1

$- 1$ kyun? All-zeros state ek fixed point hai ( $A \cdot 0 = 0$ ), isliye ye cycle se exclude ho jaati hai. Primitive kyun? Ek primitive polynomial ke roots ki maximal multiplicative order hoti hai, jo guarantee karta hai ki har non-zero state exactly ek baar visit hogi (ek maximal-length ya m-sequence).

Signature ka idea

MISR (bahut lambi) response bit-stream ko ek $n$ -bit signature mein map karta hai. Ise pre-computed golden signature se compare karo:

Match → chip PASS. Mismatch → chip FAIL.

Common Mistakes (Steel-manned)

Flashcards

Ek node testable hone ke liye konse do properties chahiye?

Controllability aur observability.

Scan flip-flop ke aage kaunsa logic insert hota hai?

Ek 2:1 MUX jo Scan Enable (SE) se select hota hai, functional D aur scan-in SI ke beech choose karta hai.

Scan FF input equation likho.

D_{f f} = \overline{S E} \cdot D + S E \cdot S I

Scan test ke teen phases ke naam batao.

Shift-in (SE=1), Capture (SE=0, 1 clock), Shift-out (SE=1).

Capture sirf ek clock cycle kyun hoti hai?

Combinational logic ke response ko shift out karne se pehle usi FFs mein latch karne ke liye.

Ek lambi scan chain ko M parallel chains mein kyun split karte hain?

Shift length N/M tak kam karne ke liye, test time ~M× ghataane ke liye.

BIST mein LFSR kya generate karta hai?

Ek pseudo-random maximal-length test-pattern sequence (PRPG).

N bits ke maximal LFSR ki period kya hoti hai aur

2^{n}

kyun nahi?

2^{n} - 1

; all-zeros state ek fixed point hai aur exclude hoti hai.

MISR kya karta hai?

Bahut saare response bits ko ek

n

-bit signature mein compact karta hai golden signature se comparison ke liye.

Aliasing kya hai aur iski probability kya hai?

Ek faulty response ka golden signature produce karna;

P \approx 2^{- n}

LFSR polynomial primitive kyun honi chahiye?

Tabhi ye saare

2^{n} - 1

non-zero states visit karta hai (maximal length).

Capture ke dauran SE timing kyun matter karti hai?

Capture ke dauran SE 0 hona chahiye; warna FF neighbour ko grab karta hai, test invalid ho jaata hai.

Recall Feynman: ek 12-saal ke bacche ko samjhao

Socho ek badi factory mein hazaron chhote chhote kamre hain, lekin poori building mein sirf kuch doors hain. Tum andar jaake har kamra check nahi kar sakte. To hum saare kamron ko ek secret conveyor belt se connect kar dete hain. Test karne ke liye, tum belt ke zariye har kamre mein ek note daalo, machines ko ek step kaam karne do, phir belt ko dobara chalao aur bahar aate saare notes padho. Yahi scan chain hai. BIST aur bhi aasaan hai: hum andar ek chhota robot banaate hain jo random notes likhta hai, jawab collect karta hai, unhe ek number mein squeeze karta hai, aur bas batata hai "sab theek hai" ya "kuch toot gaya hai."

Connections

Flip-flops and Latches — wo storage element jise scan modify karta hai.
Fault Models (Stuck-at, Bridging) — scan/BIST actually kya detect karte hain.
ATPG (Automatic Test Pattern Generation) — wo patterns produce karta hai jo shift in hote hain.
Linear Feedback Shift Registers — $GF (2)$ par LFSR/MISR ka mathematics.
JTAG Boundary Scan — board-level access ke liye related standard.
Design for Testability — umbrella methodology.