Imagine you build a huge sealed machine with millions of tiny gears (transistors). After manufacturing, some gears might be broken. But you can only touch the machine from the outside pins . How do you prove every internal gear works? DFT is the art of adding extra "access hatches" to the chip so that hidden internal faults become controllable (you can set them) and observable (you can read them out).
Design for Testability (DFT) is a set of design techniques that add controllability and observability to a circuit so that manufacturing defects can be detected efficiently after fabrication.
Controllability = ability to set an internal node to a desired logic value from the primary inputs.Observability = ability to propagate an internal node's value to a primary output where it can be measured.
WHY it matters: A modern chip has millions of flip-flops buried deep inside. Without DFT, testing them via primary I/O is a combinatorial nightmare — you'd need astronomically many test vectors. DFT makes test generation tractable and raises fault coverage toward 99%+.
We don't model every physical defect (that's infinite). Instead we use a simple proxy: the stuck-at fault model. A node is either stuck-at-0 (SA0) or stuck-at-1 (SA1) , meaning it's permanently glued to that value regardless of what drives it.
A circuit with n n n 2 n 2n 2 n single stuck-at faults (each line SA0 or SA1).
Fault coverage = faults detected by test set total testable faults = \dfrac{\text{faults detected by test set}}{\text{total testable faults}} = total testable faults faults detected by test set
HOW you detect a stuck-at fault — you need a vector that does TWO things:
Activate the fault: drive the node to the opposite of the stuck value (SA0 → drive it to 1).Sensitize a path to a primary output so the difference shows up (observability).
Combinational logic is easy — inputs directly control everything. But flip-flops hide state . To test logic feeding a flip-flop, you must first load the flip-flop through many clock cycles, then read it out through more cycles. Test complexity explodes . DFT's killer app is making flip-flops directly accessible.
Scan design converts ordinary flip-flops into scan flip-flops (a MUX + FF) that can be chained into a shift register in test mode . This lets us serially load any state into all FFs and serially read out the resulting state.
Turn all the flip-flops into beads on a string. In scan mode (SE=1) you thread new beads in one per clock; in normal mode (SE=0) they behave as the real circuit. So a hard sequential problem becomes a series of combinational tests.
HOW a scan test runs (one pattern):
Set SE=1 (shift mode). Shift in the desired FF state through Scan-In — takes N N N N N N
Set SE=0 (functional mode). Apply primary inputs, pulse clock once → combinational logic computes new FF values (capture ).
Set SE=1 again. Shift the captured values out through Scan-Out (compare against expected) — while simultaneously shifting in the next pattern.
N = 1000 N = 1000 N = 1000 P = 500 P = 500 P = 500 T ≈ ( 500 + 1 ) ( 1000 + 1 ) = 501 × 1001 ≈ 5.01 × 10 5 T \approx (500+1)(1000+1) = 501 \times 1001 \approx 5.01\times10^5 T ≈ ( 500 + 1 ) ( 1000 + 1 ) = 501 × 1001 ≈ 5.01 × 1 0 5 Why this step? Multiply patterns by per-pattern shift length; this is why designers split one long chain into many parallel scan chains — k k k N N N k k k
Instead of an expensive external tester feeding vectors, put a vector generator and a checker on the chip itself . The chip tests itself .
BIST uses an on-chip LFSR (Linear Feedback Shift Register) as a pseudo-random pattern generator (PRPG) and a MISR (Multiple-Input Signature Register) to compress all output responses into a single short signature . A wrong signature ⇒ faulty chip.
Aliasing in a MISR: a faulty response accidentally compresses to the correct signature. Probability ≈ 2 − m \approx 2^{-m} ≈ 2 − m m m m Why 2 − m 2^{-m} 2 − m With good randomness, a wrong response maps to any of 2 m 2^m 2 m
On a board , chips are soldered together — you can't probe every solder joint. Boundary scan adds a shift-register "collar" of cells around each chip's pins so you can test the wires between chips via a 4-wire interface (TDI, TDO, TCK, TMS).
Boundary scan places a boundary-scan cell on each I/O pin, chained through a TAP (Test Access Port) controlled by a 16-state FSM. Tests interconnect (open/short) faults on the PCB.
"One test vector per stuck-at fault is needed, so coverage needs 2 n 2n 2 n
Why it feels right: there are 2 n 2n 2 n Fix: a single vector detects many faults at once (fault dropping). Good ATPG achieves high coverage with far fewer than 2 n 2n 2 n
"Scan makes the circuit faster / free."
Why it feels right: scan is "just a MUX." Fix: the MUX adds delay in the functional path and area (~5–20% overhead), and scan chains increase routing . DFT trades performance/area for testability — a deliberate cost.
"An LFSR gives truly random patterns."
Why it feels right: the output looks random. Fix: it's deterministic pseudo-random — repeatable and periodic (period 2 n − 1 2^n-1 2 n − 1
"Boundary scan tests the logic inside the chip."
Why it feels right: it's a scan chain, like internal scan. Fix: boundary scan targets board-level interconnect between chips; internal scan targets internal logic . Different scopes.
Recall Click to reveal the kid versionYou built a giant robot with millions of tiny switches inside, but you sealed it shut with only a few buttons and lights on the outside. Some switches might be broken. DFT is like adding a secret zipper down the robot's back: you unzip it, slide in a note telling every switch what to be, zip up, press "GO" once, then unzip and read what each switch became . If the answer's wrong, a switch is broken! The zipper is the scan chain , and letting the robot quiz itself is BIST .
"SCAN Boundaries Bring Order to Chaos" →
S can (internal logic) · B IST (self-test on-chip) · B oundary scan (board wires) — the three pillars.
And for the two goals: "CO" = C ontrollability + O bservability (you must be able to set it and see it).
What two properties does DFT add to a circuit? Controllability (set internal nodes) and Observability (read internal nodes at outputs).
In the single stuck-at model, how many faults for n lines? 2n (each line SA0 or SA1).
Two steps to detect a stuck-at fault? Activate (drive node to opposite of stuck value) and sensitize/propagate a path to a primary output.
What turns an ordinary flip-flop into a scan flip-flop? Adding a MUX so it selects between functional data (D) and scan-in in shift mode (SE).
What does SE=1 vs SE=0 do in scan design? SE=1 = shift mode (chain acts as shift register); SE=0 = functional/capture mode.
Approx clock cycles for P patterns over a scan chain of length N? About (P+1)(N+1).
Why split one scan chain into k parallel chains? Cuts effective chain length and shift time by ~k times.
In BIST, what generates patterns and what compresses responses? LFSR/PRPG generates pseudo-random patterns; MISR compresses responses into a signature.
How many states does an n-bit maximal (primitive-polynomial) LFSR cycle through? 2^n - 1 (all-zero state excluded).
What is aliasing in a MISR and its probability? A faulty response compressing to the correct signature; probability ~ 2^(-m) for an m-bit signature.
What does boundary scan (JTAG) test? Board-level interconnect (open/short faults) between chips, via TDI/TDO/TCK/TMS and the TAP controller.
Typical cost of scan design? 5–20% area overhead plus added delay in functional path and extra routing.
Combinational Logic Testing — scan reduces sequential test to this.Automatic Test Pattern Generation (ATPG) — generates the vectors scan shifts in.Linear Feedback Shift Registers (LFSR) — engine of BIST pattern generation.Flip-Flops and Sequential Circuits — what scan modifies.JTAG / IEEE 1149.1 — boundary scan standard.Yield and Fault Coverage — economic driver of DFT.
Sequential circuits hide state
Scan flip-flops MUX plus FF
Serial shift register chain
Activate node to opposite value
Intuition Hinglish mein samjhoDekho, ek chip ke andar millions of transistors aur flip-flops hote hain, lekin bahar sirf kuch pins hote hain. Manufacturing ke baad koi internal gate kharab ho sakta hai, par aap use bahar se seedha touch nahi kar sakte. DFT ka matlab hai — design mein thoda extra hardware daalo taaki har internal node ko aap set kar sako (controllability ) aur uska value output pe padh sako (observability ). Test ke liye hum stuck-at fault model use karte hain: koi line permanently 0 (SA0) ya 1 (SA1) pe atak gayi. Fault detect karne ke liye do cheez chahiye — pehle node ko stuck value ke opposite pe drive karo (activate), phir ek path banao output tak (propagate).
Sabse bada problem sequential circuits hain, kyunki flip-flops andar state chhupa lete hain. Iska 80/20 solution hai Scan Design : har normal flip-flop ke aage ek MUX laga do, aur test mode (SE=1) mein saare flip-flops ek lambi shift register ki tarah jud jaate hain. Ab aap serially koi bhi state andar bhar sakte ho, ek clock pulse maar ke combinational logic ka result capture kar sakte ho, aur phir wahi result shift out karke check kar sakte ho. Isse mushkil sequential test ek simple combinational test ban jaata hai. Bas cost yeh hai ki MUX se thoda area aur delay badh jaata hai (5–20% overhead).
BIST mein chip khud ko test karta hai: ek LFSR pseudo-random patterns banata hai, aur MISR saare outputs ko ek chhoti si signature mein compress kar deta hai. Signature galat aaya to chip fault. Yaad rakho LFSR truly random nahi, deterministic pseudo-random hai — isliye expected signature pehle se calculate ho sakta hai. Boundary scan (JTAG) thoda alag hai — yeh chip ke andar nahi, balki board pe chips ke beech ke wires (open/short) test karta hai, 4 wires (TDI, TDO, TCK, TMS) se.
