Power grid and IR drop analysis — Hardware notes

WHY do we even care?

WHY it matters: A CMOS gate's delay grows roughly as $t_d \propto \dfrac{1}{(V_{dd}-V_{th})^{\alpha}}$ (alpha-power law, $\alpha\!\approx\!1.3$ ). Lower the local $V_{dd}$ → slower gate → possible setup timing violation. On the ground side, a raised local ground ("ground bounce") shrinks noise margins.
WHAT the grid is: A hierarchy — package bumps → top thick metal rings/straps → lower metal stripes → local rails feeding standard cells. Coarse-to-fine so resistance stays low.

Two kinds of IR drop

$\Delta V_{dynamic} = I R + L\frac{di}{dt}$

WHY the $L\,di/dt$ term appears: when a large block switches, current ramps up fast. A changing current through the package inductance $L$ creates a voltage $v_L = L\,di/dt$ that momentarily starves the supply — this is why decoupling capacitors (decaps) are placed near hot blocks: they act as local charge reservoirs that supply the fast transient so the current doesn't have to rush through $L$ .

HOW to derive the grid equations (from first principles)

We model the grid as a set of nodes (metal junctions) connected by conductances $g_{ij}=1/R_{ij}$ . At each node, apply Kirchhoff's Current Law (KCL): current in = current out.

For node $i$ with voltage $V_i$ , connected to neighbors $j$ , drawing a current-source load $I_i$ (to ground):

$\sum_{j} g_{ij}\,(V_i - V_j) = -I_i$

Why this step? Each resistor branch carries current $(V_i-V_j)/R_{ij}=g_{ij}(V_i-V_j)$ out of node $i$ . KCL says all branch currents plus the sink current balance to zero.

Stack this for all $N$ nodes → a linear system:

$\boxed{\;G\,\mathbf{V} = \mathbf{I}\;}$

where $G$ is the $N\times N$ conductance (Laplacian) matrix:

$G_{ii} = \sum_j g_{ij}$ (sum of conductances at node $i$ ),
$G_{ij} = -g_{ij}$ (off-diagonal),
$\mathbf{I}$ = injected currents (supply pins are known-voltage sources, loads are current sinks).

Why this is beautiful: $G$ is exactly the same graph Laplacian used everywhere in networks. Solving $G\mathbf V=\mathbf I$ gives every node voltage; IR drop at node $i$ is $V_{dd}-V_i$ .

For dynamic analysis we add capacitance/inductance and integrate over time: $G\mathbf{V}(t) + C\,\dot{\mathbf V}(t) = \mathbf I(t)$

Figure — Power grid and IR drop analysis

Worked Example 1 — single wire segment

A power rail carries $I = 20\text{ mA}$ through a wire of resistance $R = 2\ \Omega$ .

$\Delta V = IR = 0.020 \times 2 = 0.04\text{ V} = 40\text{ mV}$

Why this step? Direct Ohm's law — one branch, one current. If $V_{dd}=1.0$ V, the gate sees $0.96$ V. If the drop budget is $5\%$ ( $50$ mV), we pass (40 < 50).

Worked Example 2 — distributed rail (why widening the wire helps)

A rail of total resistance $R$ feeds $n$ equal cells, each drawing $I$ , at points $1,2,\dots,n$ along the wire. Segment $k$ (nearest the pin is segment 1) carries the current of all cells beyond it.

Current in segment $k$ = $(n-k+1)I$ . With per-segment resistance $r=R/n$ :

$\Delta V_{end} = \sum_{k=1}^{n} r\,(n-k+1)I = rI\sum_{m=1}^{n} m = \frac{R}{n}\,I\,\frac{n(n+1)}{2}=\frac{IR(n+1)}{2}$

Why this step? The cell farthest from the pin suffers the accumulated drop of every segment its current traversed. For large $n$ , $\Delta V_{end}\approx \tfrac12 I R n = \tfrac12 (\text{total }I)(R)$ — half of "all current through all resistance", a classic distributed result.

HOW to fix it: Halving $R$ (wider/thicker metal, more straps) halves the drop. Feeding from both ends roughly quarters it (two parallel halves, each shorter).

Worked Example 3 — decap sizing intuition (dynamic)

A block needs a transient charge $Q$ during a fast switch of duration $\Delta t$ , and we allow a droop $\Delta V$ . Charge from a decap: $Q = C\,\Delta V$ .

If the block draws $I=50$ mA for $\Delta t=100$ ps and we allow $\Delta V=30$ mV to come from the cap: $C = \frac{I\,\Delta t}{\Delta V} = \frac{0.05 \times 100\times10^{-12}}{0.03} \approx 167\text{ pF}$

Why this step? The cap dumps $Q=I\Delta t$ locally so current needn't rush through $L$ ; $C=Q/\Delta V$ from $Q=CV$ .

Common mistake Steel-manned misconceptions

"Bigger current always means bigger IR drop, so low-power blocks are safe." Why it feels right: $\Delta V=IR$ — small $I$ , small drop. The fix: IR drop depends on local current density and the resistance path, not just total current. A block far from the pin with a thin rail can droop badly even at modest current. Also dynamic droop is driven by $di/dt$ , not steady $I$ — a block can be low-average-power yet switch violently.

"IR drop is a wire problem, timing is a separate problem." Why it feels right: They're different tools/flows. The fix: IR drop is a timing problem — droop lowers $V_{dd}$ which increases cell delay. Modern sign-off does IR-drop-aware timing (voltage-derated delays).

"Static analysis is enough." Why it feels right: It's fast and gives the worst average. The fix: Peak dynamic droop (with $L\,di/dt$ ) is often 2–3× larger than static and is what actually fails silicon. You need both.

Recall Feynman: explain to a 12-year-old

Imagine a long garden hose feeding lots of sprinklers. The water pressure at the far sprinkler is weaker because the hose "eats" some pressure along the way. In a chip, "pressure" is voltage, "water" is electric current, and the "hose" is the metal wires. If a wire is thin (a skinny hose), the far-away gates get weak voltage and get slow and lazy. Engineers fix it by using fatter pipes (thicker/wider metal), adding more pipes (mesh), feeding from both ends, and putting little water tanks (capacitors) right next to thirsty parts so they don't have to gulp from the far tap all at once.

Active Recall

What is IR drop?

The supply-voltage reduction

\Delta V = IR

caused by current flowing through the resistance of power/ground metal wires.

Why does IR drop hurt timing?

Lower local

V_{dd}

increases CMOS gate delay (

t_d \propto 1/(V_{dd}-V_{th})^{\alpha}

), potentially causing setup violations.

Static vs dynamic IR drop?

Static uses average current on a pure resistive network (

IR

); dynamic uses instantaneous switching current on an RLC network and adds the

L\,di/dt

inductive term.

What matrix equation governs the power grid?

G\mathbf V = \mathbf I

, where

G

is the conductance (graph Laplacian) matrix from KCL at every node.

How is the conductance matrix built?

G_{ii}=\sum_j g_{ij}

G_{ij}=-g_{ij}

, with

g_{ij}=1/R_{ij}

for each resistor branch.

Where does the

L\,di/dt

term come from?

Fast current ramp through package/bond-wire inductance

L

produces

v_L=L\,di/dt

, momentarily starving the supply.

What do decoupling capacitors do?

Act as local charge reservoirs supplying fast transient current so it needn't rush through

L

, reducing dynamic droop; sized by

C=I\Delta t/\Delta V

End-of-rail drop feeding n equal cells?

\Delta V_{end}=\dfrac{IR(n+1)}{2}\approx \tfrac12 I_{total}R

for large

n

Two design fixes for IR drop?

Lower resistance (wider/thicker metal, denser mesh, dual-end feed) and add decaps for dynamic droop.

Typical IR-drop budget?

Around 5% of

V_{dd}

(static + dynamic combined) as a sign-off rule of thumb.

Connections

CMOS gate delay and alpha-power law
Kirchhoff's Current Law
Graph Laplacian matrix
Decoupling capacitors and PDN design
Static timing analysis (STA)
Electromigration and current density
Package and bond-wire inductance

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, chip ke andar power grid ek bade resistor ke jaal jaisa hota hai jo package ke pins se lekar crore transistors tak current pahunchata hai. Problem yeh hai ki har metal wire ki thodi si resistance hoti hai, aur jab current us resistance se guzarta hai to Ohm ke law se voltage gir jaata hai — yahi hai IR drop ( $\Delta V = IR$ ). Matlab jo gate pin se door hai, use ideal $V_{dd}$ se kam voltage milta hai.

Iska seedha asar timing par padta hai. Kam voltage matlab gate slow, aur slow gate matlab setup violation — chip fail. Isiliye IR drop koi alag "wire ka problem" nahi, yeh actually timing ka hi problem hai. Do type hote hain: static (average current, sirf resistive network, $IR$ ) aur dynamic (instantaneous switching current, RLC network, jismein $L\,di/dt$ ka extra term aata hai). Jab bada block ek saath switch karta hai to current tezi se badhta hai, aur package inductance $L$ se $L\,di/dt$ voltage droop banta hai — yeh static se 2-3 guna bada ho sakta hai.

Solve kaise karte hain? Har node par KCL lagao, saare nodes ka system banao: $G\mathbf V = \mathbf I$ , jahan $G$ conductance (Laplacian) matrix hai. Isse har node ka voltage nikal aata hai, aur IR drop $= V_{dd} - V_i$ . Fix karne ke liye: metal ko chauda/mota karo (resistance kam), mesh dense karo, dono taraf se feed karo, aur hot blocks ke paas decoupling capacitors lagao jo local charge tank ki tarah kaam karke fast transient supply karte hain — taaki current ko door se $L$ ke through daudna na pade. Rule of thumb: total budget lagbhag 5% of $V_{dd}$ .

Test yourself — VLSI Design

Connections