Power grid and IR drop analysis — Hinglish notes

4.2.12 · Hardware › VLSI Design

WHY hum iski parwah karte hain?

WHY yeh matter karta hai: Ek CMOS gate ki delay roughly aise badhti hai $t_{d} \propto \frac{1}{( V _{dd} - V _{t h} ) ^{α}}$ (alpha-power law, $α \approx 1.3$ ). Local $V_{dd}$ kam karo → gate slow → possible setup timing violation. Ground side par, ek raised local ground ("ground bounce") noise margins ko shrink kar deta hai.
WHAT grid hai: Ek hierarchy — package bumps → top thick metal rings/straps → lower metal stripes → local rails jo standard cells ko feed karti hain. Coarse-to-fine taaki resistance kam rahe.

Do tarah ka IR drop

$Δ V_{d y nami c} = I R + L \frac{d i}{d t}$

WHY $L d i / d t$ term aata hai: Jab ek bada block switch karta hai, current fast ramp up hoti hai. Package inductance $L$ se badlata current ek voltage $v_{L} = L d i / d t$ create karta hai jo supply ko momentarily starve kar deta hai — isliye decoupling capacitors (decaps) hot blocks ke paas rakhe jaate hain: woh local charge reservoirs ki tarah kaam karte hain jo fast transient ko supply karte hain taaki current $L$ se rush na kare.

HOW grid equations derive karte hain (first principles se)

Hum grid ko nodes (metal junctions) ka ek set maante hain jo conductances $g_{ij} = 1/ R_{ij}$ se connected hain. Har node par Kirchhoff's Current Law (KCL) apply karo: current in = current out.

Node $i$ ke liye jiska voltage $V_{i}$ hai, jo neighbors $j$ se connected hai, aur current-source load $I_{i}$ draw kar raha hai (ground ki taraf):

$\sum_{j} g_{ij} (V_{i} - V_{j}) = - I_{i}$

Yeh step kyun? Har resistor branch node $i$ se $(V_{i} - V_{j}) / R_{ij} = g_{ij} (V_{i} - V_{j})$ current carry karta hai. KCL kehta hai ki saari branch currents aur sink current zero balance karti hain.

Sabhi $N$ nodes ke liye stack karo → ek linear system:

$G V = I$

jahan $G$ ek $N \times N$ conductance (Laplacian) matrix hai:

$G_{ii} = \sum_{j} g_{ij}$ (node $i$ par conductances ka sum),
$G_{ij} = - g_{ij}$ (off-diagonal),
$I$ = injected currents (supply pins known-voltage sources hain, loads current sinks hain).

Yeh kyun beautiful hai: $G$ exactly wahi graph Laplacian hai jo networks mein har jagah use hota hai. $G V = I$ solve karne se har node voltage milti hai; node $i$ par IR drop hai $V_{dd} - V_{i}$ .

Dynamic analysis ke liye hum capacitance/inductance add karte hain aur time par integrate karte hain: $G V (t) + C \dot{V} (t) = I (t)$

Figure — Power grid and IR drop analysis

Worked Example 1 — single wire segment

Ek power rail $I = 20 mA$ current carry karta hai wire ki resistance $R = 2 Ω$ se hoke.

$Δ V = I R = 0.020 \times 2 = 0.04 V = 40 mV$

Yeh step kyun? Direct Ohm's law — ek branch, ek current. Agar $V_{dd} = 1.0$ V hai, toh gate $0.96$ V dekhta hai. Agar drop budget $5%$ ( $50$ mV) hai, toh hum pass karte hain (40 < 50).

Worked Example 2 — distributed rail (kyun wire wide karna help karta hai)

Ek rail jis ki total resistance $R$ hai, wire ke saath $1, 2, \dots, n$ points par $n$ equal cells ko feed karti hai, jahan har cell $I$ draw karti hai. Segment $k$ (pin ke sabse paas wala segment 1 hai) uske aage ke saari cells ka current carry karta hai.

Segment $k$ mein current = $(n - k + 1) I$ . Per-segment resistance $r = R / n$ ke saath:

$Δ V_{e n d} = \sum_{k = 1}^{n} r (n - k + 1) I = r I \sum_{m = 1}^{n} m = \frac{R}{n} I \frac{n ( n + 1 )}{2} = \frac{I R ( n + 1 )}{2}$

Yeh step kyun? Pin se sabse door wala cell accumulated drop suffer karta hai har us segment ka jisse uska current guzra. Bade $n$ ke liye, $Δ V_{e n d} \approx \frac{1}{2} I R n = \frac{1}{2} (total I) (R)$ — "saari current saari resistance se" ka aadha — ek classic distributed result.

HOW fix karte hain: $R$ ko half karo (wider/thicker metal, zyada straps) toh drop bhi half. Dono ends se feed karne par roughly quarter ho jaata hai (do parallel halves, har ek shorter).

Worked Example 3 — decap sizing intuition (dynamic)

Ek block ko ek fast switch ke dauran duration $Δ t$ mein transient charge $Q$ chahiye, aur hum droop $Δ V$ allow karte hain. Ek decap se charge: $Q = C Δ V$ .

Agar block $I = 50$ mA draw karta hai $Δ t = 100$ ps ke liye aur hum $Δ V = 30$ mV cap se aane dete hain: $C = \frac{I Δ t}{Δ V} = \frac{0.05 \times 100 \times 1 0 ^{- 12}}{0.03} \approx 167 pF$

Yeh step kyun? Cap locally $Q = I Δ t$ dump karta hai taaki current $L$ se rush na kare; $Q = C V$ se $C = Q /Δ V$ .

Common mistake Steel-manned misconceptions

"Zyada current matlab hamesha zyada IR drop, isliye low-power blocks safe hain." Kyun sahi lagta hai: $Δ V = I R$ — chhota $I$ , chhota drop. Fix: IR drop depend karta hai local current density aur resistance path par, sirf total current par nahi. Pin se door ek block thin rail ke saath modest current par bhi buri tarah droop kar sakta hai. Aur dynamic droop $d i / d t$ se drive hota hai, steady $I$ se nahi — ek block low-average-power ho sakta hai phir bhi violently switch kar sakta hai.

"IR drop ek wire problem hai, timing ek alag problem hai." Kyun sahi lagta hai: Yeh alag tools/flows hain. Fix: IR drop hai hi ek timing problem — droop $V_{dd}$ ko lower karta hai jo cell delay badhata hai. Modern sign-off IR-drop-aware timing karta hai (voltage-derated delays).

"Static analysis kaafi hai." Kyun sahi lagta hai: Yeh fast hai aur worst average deta hai. Fix: Peak dynamic droop ( $L d i / d t$ ke saath) aksar static se 2–3× zyada hota hai aur wahi actually silicon fail karta hai. Dono chahiye.

Recall Feynman: 12-saal ke bacche ko samjhao

Socho ek lamba garden hose bahut saare sprinklers ko feed kar raha hai. Door wale sprinkler par water pressure kamzor hoti hai kyunki hose raaste mein kuch pressure "kha" leta hai. Chip mein, "pressure" voltage hai, "paani" electric current hai, aur "hose" metal wires hain. Agar wire thin hai (patle hose), toh door ke gates ko kamzor voltage milti hai aur woh slow aur lazy ho jaate hain. Engineers isko fix karte hain mote pipes (thicker/wider metal) use karke, zyada pipes (mesh) add karke, dono ends se feed karke, aur chhote paani ke tanks (capacitors) thirsty parts ke bilkul paas rakhke taaki unhe door ke tap se ek saath ghut-ghut nahi peena pade.

Active Recall

IR drop kya hai?

Supply-voltage reduction

Δ V = I R

jo power/ground metal wires ki resistance se current flow hone par hoti hai.

IR drop timing ko kyun hurt karta hai?

Lower local

V_{dd}

CMOS gate delay badhata hai (

t_{d} \propto 1/ (V_{dd} - V_{t h})^{α}

), jo potentially setup violations cause karta hai.

Static vs dynamic IR drop?

Static average current use karta hai pure resistive network par (

I R

); dynamic instantaneous switching current use karta hai RLC network par aur

L d i / d t

inductive term add karta hai.

Kaun sa matrix equation power grid govern karta hai?

G V = I

, jahan

G

conductance (graph Laplacian) matrix hai jo har node par KCL se bani hai.

Conductance matrix kaise build hoti hai?

G_{ii} = \sum_{j} g_{ij}

G_{ij} = - g_{ij}

, har resistor branch ke liye

g_{ij} = 1/ R_{ij}

ke saath.

L d i / d t

term kahaan se aata hai?

Package/bond-wire inductance

L

se fast current ramp

v_{L} = L d i / d t

produce karta hai, jo supply ko momentarily starve kar deta hai.

Decoupling capacitors kya karte hain?

Local charge reservoirs ki tarah kaam karte hain jo fast transient current supply karte hain taaki use

L

se rush na karna pade, dynamic droop reduce karta hai;

C = I Δ t /Δ V

se sized hota hai.

n equal cells ko feed karne par end-of-rail drop?

Δ V_{e n d} = \frac{I R ( n + 1 )}{2} \approx \frac{1}{2} I_{t o t a l} R

bade

n

ke liye.

IR drop ke liye do design fixes?

Resistance kam karo (wider/thicker metal, denser mesh, dual-end feed) aur dynamic droop ke liye decaps add karo.

Typical IR-drop budget?

V_{dd}

ka lagbhag 5% (static + dynamic combined) ek sign-off rule of thumb ki tarah.

Connections

CMOS gate delay and alpha-power law
Kirchhoff's Current Law
Graph Laplacian matrix
Decoupling capacitors and PDN design
Static timing analysis (STA)
Electromigration and current density
Package and bond-wire inductance