Timing analysis basics (static timing)

WHAT is STA?

Why not just simulate? Simulation only checks the paths that the chosen test vectors exercise. STA checks all paths structurally, so it can guarantee timing closure. That's the 80/20 win: one static analysis replaces astronomically many input-vector simulations.

The building blocks

Figure — Timing analysis basics (static timing)

HOW: deriving the setup constraint from scratch

Derivation. Consider two flip-flops FF1 (launch) → combinational logic → FF2 (capture), same clock.

Step 1 — When does data leave FF1? At the launch edge (time $0$ ), plus the flop's own delay: $t_{launch\_data} = t_{cq}$ Why this step? Q can't change instantly; it changes $t_{cq}$ after the edge.

Step 2 — When does data arrive at FF2's input? Add the logic delay: $t_{arrive} = t_{cq} + t_{comb}$ Why? The signal must physically propagate through the gates.

Step 3 — The deadline at FF2. The next capture edge is at $T_{clk}$ . Data must be stable $t_{su}$ before it: $t_{deadline} = T_{clk} - t_{su}$ Why? Setup demands early arrival.

Step 4 — Require arrive ≤ deadline: $t_{cq} + t_{comb} \le T_{clk} - t_{su}$

The slowest (longest-delay) path sets the max frequency → it's the critical path. Setup uses $t_{comb,max}$ .

HOW: deriving the hold constraint from scratch

Derivation. Both flops see the same edge (at time $0$ for hold analysis).

Step 1 — Earliest the new data reaches FF2: $t_{arrive} = t_{cq} + t_{comb,min}$ Why $min$ ? We fear the fastest path here — the earliest possible disturbance.

Step 2 — FF2 needs the old data held until $t_h$ after the edge: $t_{arrive} \ge t_h$

Slack: the pass/fail number

Worked examples

Common mistakes

Active recall

Recall Why is STA "static"?

Because it analyzes worst-case path delays from the circuit structure without needing input vectors or logic simulation.

Recall Which delay do setup and hold each use?

Setup → maximum (longest) path delay. Hold → minimum (shortest) path delay.

Recall Does slowing the clock fix a hold violation?

No. Hold is independent of $T_{clk}$ ; you must add data-path delay.

Recall Feynman: explain to a 12-year-old

Imagine passing a note in class between two desks, and every "click" the teacher makes, the note must be sitting on the next desk ready. Setup: the note has to arrive a little before the click, or the friend can't read it in time. Hold: the note must not zoom over so fast that it lands during the same click and messes up the note that's still being read. If the notes are too slow → wait longer between clicks (slower clock). If they're too fast → make them take a scenic route.

Forecast-then-Verify

Before reading Example 2, predict: at 250 MHz will the 200-MHz-capable circuit pass? (No — negative slack.) Before Example 4, predict skew's effect. Confirm against the formulas.

Connections

What does STA stand for and check?

Static Timing Analysis; checks all register-to-register paths against setup/hold constraints without simulation.

Setup constraint inequality

t_{cq}+t_{comb,max}+t_{su}\le T_{clk}

t_{skew}

if any).

Hold constraint inequality

t_{cq}+t_{comb,min}\ge t_h

t_{skew}

if any).

Formula for max clock frequency

f_{max}=1/(t_{cq}+t_{comb,max}+t_{su})

Setup uses which path delay?

Maximum (longest / critical) path.

Hold uses which path delay?

Minimum (shortest) path.

Does clock period appear in the hold equation?

No — hold is

T_{clk}

-independent.

Definition of setup slack

T_{clk}-(t_{cq}+t_{comb}+t_{su})

; positive = pass.

How to fix a hold violation?

Add delay (buffers) to the short data path, not by slowing the clock.

Effect of positive clock skew (

t_{capture}

later)?

Relaxes setup, tightens hold.

Why does STA beat simulation for timing?

It is exhaustive over all paths structurally; simulation only covers exercised vectors.

What causes metastability if setup/hold is violated?

Flip-flop samples unstable data and may hover between 0 and 1.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, digital circuit ek race hai clock ke against. Har clock edge par data ko ek flip-flop se nikal kar, combinational logic ke through travel karke, agle flip-flop tak settle ho jana chahiye — before the next edge. Static Timing Analysis (STA) yahi check karta hai, lekin bina simulation chalaye. "Static" ka matlab: input values ki zarurat nahi, sirf circuit ka structure aur uske delays dekhte hain. Isliye ye saare paths ek saath check kar leta hai — 80/20 fayda.

Do main rules hain. Setup: $t_{cq}+t_{comb,max}+t_{su}\le T_{clk}$ . Yani launch flop ka clock-to-Q delay, plus sabse lamba (slowest) logic path, plus setup margin — ye sab clock period ke andar fit hone chahiye. Sabse slow path ko critical path kehte hain, aur wahi $f_{max}$ decide karta hai: $f_{max}=1/(t_{cq}+t_{comb,max}+t_{su})$ . Hold: $t_{cq}+t_{comb,min}\ge t_h$ . Yaha fastest path ka darr hai — naya data itni tezi se na aa jaye ki same edge par purani value corrupt kar de.

Sabse important baat, jo exam mein log galat karte hain: setup fail ho toh clock slow karke fix kar sakte ho, lekin hold fail ho toh clock slow karne se kuch nahi hota — kyunki hold equation mein $T_{clk}$ hai hi nahi! Hold fix karne ke liye short path mein delay (buffers) daalna padta hai. Aur yaad rakho: setup = longest path, hold = shortest path. Slack positive matlab pass, negative matlab violation.

Agar ye clear ho gaya, toh timing closure, pipelining, aur clock skew ka pura concept aasan lagega. Basically har cheez isi race ke around ghumti hai.

WHAT is STA?

The building blocks

HOW: deriving the setup constraint from scratch

HOW: deriving the hold constraint from scratch

Slack: the pass/fail number

Worked examples

Common mistakes

Active recall

Forecast-then-Verify

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — HDL & Digital Design Flow

Connections