Level 2 — RecallHDL & Digital Design Flow

HDL & Digital Design Flow

⏱ 30 minutes40 marksprintable — key stays hidden on paper

Level: 2 — Recall (definitions, standard problems, short derivations) Time Limit: 30 minutes Total Marks: 40

Instructions

Answer all questions. Show working where derivations are required. Use correct Verilog syntax in code answers.

Q1. Define the following terms in one sentence each: (a) RTL, (b) netlist, (c) testbench. (3 marks)

Q2. State the key difference between blocking (=) and non-blocking (<=) assignments in Verilog, and name which one should be used for modelling sequential (clocked) logic. (3 marks)

Q3. Write a Verilog module for a 2-to-1 multiplexer named mux2 with inputs a, b, sel and output y, using a continuous assignment (assign). (4 marks)

Q4. For the following always block, state whether it describes combinational or sequential logic and justify your answer:

always @(posedge clk)
    q <= d;

(3 marks)

Q5. Complete the sensitivity list for this combinational logic block and explain why it must be complete:

always @(______)
    y = (a & b) | c;

(4 marks)

Q6. List four differences between FPGA and ASIC design flows (one per line). (4 marks)

Q7. A combinational path has the following delays: input-to-first-gate = 1.2 ns, three gates in series at 0.8 ns each, and final routing = 0.9 ns. Compute the total propagation delay of this path. (4 marks)

Q8. A register-to-register path has a combinational logic delay of $t_{logic} = 6\text{ ns}$ , a clock-to-Q delay $t_{cq} = 0.5\text{ ns}$ , and a setup time $t_{su} = 0.3\text{ ns}$ . (a) Write the expression for the minimum clock period (ignore clock skew). (2 marks) (b) Compute the minimum clock period. (2 marks) (c) Compute the maximum operating frequency in MHz. (2 marks)

Q9. Define the critical path of a synchronous circuit and state how it relates to the maximum clock frequency. (3 marks)

Q10. In one sentence each, describe the purpose of these steps in the design flow: (a) simulation, (b) synthesis, (c) static timing analysis. (3 marks)

END OF PAPER

Answer keyMark scheme & solutions

Q1. (3 marks) — 1 mark each

(a) RTL (Register Transfer Level): an abstraction describing a circuit in terms of the flow of data between registers and the logic operations performed on that data. (captures behaviour, not gates)
(b) Netlist: a list of logic gates/cells and their interconnections, produced by synthesis. (structural description)
(c) Testbench: a non-synthesizable HDL module that applies stimulus to a design under test and checks/observes its outputs during simulation.

Q2. (3 marks)

Blocking (=): executes sequentially/immediately; the RHS is evaluated and assigned before the next statement runs. (1)
Non-blocking (<=): all RHS values are evaluated first, then assignments happen simultaneously at the end of the time step. (1)
Non-blocking should be used for sequential (clocked) logic to correctly model concurrent register updates. (1)

Q3. (4 marks)

module mux2 (
    input  a,
    input  b,
    input  sel,
    output y
);
    assign y = sel ? b : a;
endmodule

Marks: module header + ports (1), correct input/output declarations (1), correct assign with conditional (1), correct logic (sel=1→b, sel=0→a) (1). (Accept y = (sel & b) | (~sel & a).)

Q4. (3 marks)

This describes sequential logic. (1)
Justification: triggered on posedge clk (an edge), so the output updates only on the clock edge. (1)
Uses non-blocking <= and stores d into q, i.e. a D flip-flop / register. (1)

Q5. (4 marks)

Completed line: always @(a, b, c) or always @(*). (2)
Explanation: the sensitivity list must include all signals read on the RHS (a, b, c) so that the block re-evaluates whenever any input changes. (1)
If incomplete, simulation produces incorrect behaviour (stale outputs / simulation–synthesis mismatch), because it acts like an unintended latch/misses updates. (1) (@(*) recommended to avoid errors.)

Q6. (4 marks) — 1 mark per valid difference (any four)

FPGA is reprogrammable/reconfigurable; ASIC is fixed once fabricated.
FPGA has low/no NRE cost; ASIC has high NRE (mask) cost.
FPGA suits low volume/prototyping; ASIC is cost-effective at high volume.
FPGA has shorter time-to-market; ASIC needs longer fabrication.
ASIC gives higher performance / lower power / smaller area than FPGA.
FPGA maps to LUTs/CLBs; ASIC maps to standard-cell gates.

Q7. (4 marks) $t_{total} = 1.2 + (3 \times 0.8) + 0.9$

Gate chain: $3 \times 0.8 = 2.4$ ns (1)
Sum: $1.2 + 2.4 + 0.9 = 4.5$ ns (2)
Total delay = 4.5 ns (1)

Q8. (6 marks)

(a) $T_{min} = t_{cq} + t_{logic} + t_{su}$ (2)
(b) $T_{min} = 0.5 + 6 + 0.3 = 6.8$ ns (2)
(c) $f_{max} = 1/T_{min} = 1/6.8\text{ ns} = 0.14706$ GHz $\approx 147.06$ MHz (2)

Q9. (3 marks)

Critical path = the register-to-register (or I/O) path with the longest total propagation delay in the circuit. (2)
It sets the minimum clock period; hence $f_{max} = 1/T_{critical}$ — the slowest path limits the maximum clock frequency. (1)

Q10. (3 marks) — 1 mark each

(a) Simulation: verify the functional correctness of the design against expected behaviour before hardware implementation.
(b) Synthesis: convert RTL HDL into a gate-level netlist mapped to a target technology library.
(c) Static timing analysis (STA): verify that all timing paths meet setup/hold constraints across the design without needing input vectors.

[
  {"claim":"Q7 total path delay is 4.5 ns","code":"result = (1.2 + 3*0.8 + 0.9) == 4.5"},
  {"claim":"Q8b minimum clock period is 6.8 ns","code":"result = (0.5 + 6 + 0.3) == 6.8"},
  {"claim":"Q8c max frequency approx 147.06 MHz","code":"Tmin=6.8e-9; fmax=1/Tmin; result = abs(fmax/1e6 - 147.0588) < 0.01"},
  {"claim":"Q8 relation fmax = 1/Tmin holds numerically","code":"result = abs((1/6.8e-9)*6.8e-9 - 1) < 1e-9"}
]