HDL & Digital Design Flow

Question 1 (14 marks)

(a) (5 marks) The block uses blocking (=) assignments executed sequentially within one edge event.

• a = din; → a immediately becomes din.
• b = a; → b immediately becomes the new a = din.
• q_out = b; → q_out immediately becomes din.

So on each edge all three variables collapse to the current din. (2) Synthesis: the tool sees that a and b are read only after being written in the same block, so they are optimised away; only one flip-flop (for q_out) remains. (2) It is therefore a single-register delay, not a 3-stage shift register. (1)

(b) (5 marks)

always @(posedge clk) begin
  a     <= din;
  b     <= a;
  q_out <= b;
end

Use non-blocking (<=). (2) Non-blocking assignments schedule all RHS evaluations using old values, then update simultaneously at the end of the time step, correctly modelling parallel flip-flops that each capture the previous stage's value. (2) This yields three cascaded registers → 3-stage shift register. (1)

(c) (4 marks) Pipeline (a,b,q_out), initial 0,0,0. din sequence 1,0,1,1,0.

q_out sequence = 0, 0, 1, 0, 1. (4; deduct 1 per error)

Question 2 (12 marks)

(a) (6 marks)

module mux4 (input d0, d1, d2, d3, input [1:0] sel, output reg y);
  always @(*) begin
    case (sel)
      2'b00: y = d0;
      2'b01: y = d1;
      2'b10: y = d2;
      2'b11: y = d3;
      default: y = 1'b0;
    endcase
  end
endmodule

Marks: correct interface/reg output (1), always@(*) (1), case syntax (1), four correct mappings (2), default/completeness (1).

(b) (4 marks) With one branch missing, y is not assigned for sel = 2'b11. In an always @(*) block, an unassigned variable retains its previous value, so the synthesiser infers a latch on y. (2) Even though sel is only 2 bits, 2'b11 is a legal, reachable value; the incomplete case is still not fully specified, producing an unintended level-sensitive latch — a common source of timing/glitch bugs. (2)

(c) (2 marks)

assign y = sel[1] ? (sel[0] ? d3 : d2) : (sel[0] ? d1 : d0);

Question 3 (16 marks)

(a) (6 marks) Setup inequality (skew adds to available time on launch side / here skew delays capture clock, relaxing setup): $t_{cq} + t_{logic} + t_{su} \le T + t_{skew}$ $T_{min} = t_{cq} + t_{logic} + t_{su} - t_{skew} = 0.4 + 3.1 + 0.3 - 0.25 = 3.55\ \text{ns}$ (4) $f_{max} = 1/3.55\text{ns} = 281.7\ \text{MHz}$ (2)

(b) (5 marks) Hold inequality (capture clock later by skew → tougher): $t_{cq} + t_{cd,logic} \ge t_h + t_{skew}$ LHS $= 0.4 + 0.5 = 0.9$ ns; RHS $= 0.2 + 0.25 = 0.45$ ns. (3) Slack $= 0.9 - 0.45 = 0.45$ ns $> 0$ → hold constraint satisfied. (2)

(c) (5 marks) Split logic into two balanced halves: each stage logic $= 3.1/2 = 1.55$ ns. New per-stage requirement (ignore skew): $T_{min} = t_{cq} + (t_{logic}/2) + t_{su} = 0.4 + 1.55 + 0.3 = 2.25\ \text{ns}$ (3) $f_{max} = 1/2.25\text{ns} = 444.4\ \text{MHz}$ Required 350 MHz → period 2.857 ns > 2.25 ns. 350 MHz is now met (with 0.607 ns slack). (2)

Question 4 (10 marks)

(a) (7 marks)

module tb_adder4;
  reg  [3:0] a, b;
  wire [4:0] sum;
  integer errors = 0;
 
  adder4 dut (.a(a), .b(b), .sum(sum));
 
  task check;
    input [3:0] ta, tb;
    reg [4:0] exp;
    begin
      a = ta; b = tb; #1;
      exp = ta + tb;
      if (sum === exp)
        $display("PASS: %0d + %0d = %0d", ta, tb, sum);
      else begin
        $display("FAIL: %0d + %0d got %0d exp %0d", ta, tb, sum, exp);
        errors = errors + 1;
      end
    end
  endtask
 
  initial begin
    check(4'd3, 4'd5);
    check(4'd15, 4'd15);
    check(4'd0, 4'd9);
    $display("Total errors = %0d", errors);
    $finish;
  end
endmodule

Marks: instantiation (1), ≥3 vectors (1), behavioural expected value (2), comparison + PASS/FAIL (2), $finish (1).

(b) (3 marks) Self-checking testbenches produce a machine-readable PASS/FAIL verdict, so they can run unattended in CI with no human waveform inspection (1); they scale to thousands of vectors and catch regressions automatically (1); and they give an objective, reproducible reference model rather than error-prone visual judgement (1).

Question 5 (8 marks)

(a) (6 marks) — any three, 2 each:

• Clocking/reset: FPGA uses dedicated global clock buffers and often async/vendor-specific reset; ASIC needs a custom clock tree, and synchronous reset strategy chosen for area/timing.
• Memory/IP mapping: FPGA block-RAM/DSP primitives must be replaced by ASIC RAM compilers / standard-cell macros.
• Timing closure: ASIC needs full physical synthesis, place-and-route, and sign-off STA with parasitic extraction, whereas FPGA timing is bounded by fixed fabric.
• Design-for-test: ASIC requires scan-chain/BIST insertion not needed on FPGA.
• Power/area optimisation: ASIC allows and demands gate-level/library-specific optimisation, multi-Vt cells, etc.

(b) (2 marks)

• Synthesis: the process that translates RTL (behavioural HDL) into a network of logic gates/flip-flops from a target technology library. (1)
• Gate-level netlist: a structural description listing the actual library cells and their interconnections that implement the design. (1)

[
  {"claim":"Q3a Tmin = tcq+tlogic+tsu-skew = 3.55 ns","code":"Tmin=0.4+3.1+0.3-0.25; result=abs(Tmin-3.55)<1e-9"},
  {"claim":"Q3a fmax approx 281.7 MHz","code":"f=1/(3.55e-9); result=abs(f-281.69e6)<1e5"},
  {"claim":"Q3b hold slack = 0.45 ns positive","code":"slack=(0.4+0.5)-(0.2+0.25); result=abs(slack-0.45)<1e-9 and slack>0"},
  {"claim":"Q3c pipelined Tmin=2.25 ns meets 350MHz (2.857 ns period)","code":"Tmin=0.4+3.1/2+0.3; result=abs(Tmin-2.25)<1e-9 and Tmin<(1/350e6)*1e9"}
]