Synthesis to gate-level netlist

WHAT is synthesis?

Three inputs are always required:

1. RTL source — your always/process behavioral code.
2. Technology library (.lib) — the menu of available gates, each with delay, area, power.
3. Constraints (SDC) — clock period, input/output delays, area budget, etc.

The output is a netlist: still Verilog syntactically, but now it contains no +, if, or always @(posedge) behavior — only instantiated cells like AND2X1 u5 (.A(...), .B(...), .Y(...));.

HOW it works — the four stages

RTL ──► [1 Elaboration] ──► [2 Translation to      ──► [3 Technology  ──► [4 Optimization] ──► Netlist
         + parse/check       generic Boolean/RTL         mapping to
                             (GTECH) logic]              real .lib cells]

Stage 1 — Elaboration/Parsing. Read HDL, check syntax, resolve parameters, build a hierarchy. Why: nothing else can happen until the tool has an internal model.

Stage 2 — Translation to generic logic (GTECH). Behavior → technology-independent Boolean network. assign y = a & b | c; becomes an abstract AND/OR graph. Why: optimize Boolean logic before committing to a specific vendor's gates.

Stage 3 — Technology mapping. Cover the Boolean network with actual library cells (e.g. replace generic 3-input logic with an AOI21X1 if one exists). Why: only real cells have real delay/area, so we must pick them to know if timing is met.

Stage 4 — Optimization. Restructure logic, resize/buffer cells, balance paths to satisfy the SDC constraints. Why: the first legal mapping is rarely the fastest or smallest.

The core numbers: timing closure

Synthesis exists mostly to hit timing. Derive the key inequality from scratch.

Setup: signal launched by FF1 on a clock edge, must be captured by FF2 on the next edge, one clock period $T$ later.

Time available for the data to travel = one clock period. But two things eat into it:

• The launching flop doesn't output instantly: clock-to-Q delay $t_{cq}$.
• The capturing flop needs data steady before its edge: setup time $t_{su}$.

So the time left for the combinational logic (plus a margin/uncertainty) is:

$T - t_{cq} - t_{su} - t_{unc}$

Requiring the actual logic delay to fit:

Why each term: $t_{cq}$ delays the start, $t_{logic}$ is what synthesis controls (by choosing gates), $t_{su}$ shifts the deadline earlier, $t_{unc}$ covers clock jitter/skew estimate. Everything must fit inside one period $T$.

How synthesis reacts to negative slack: upsize gates (faster but bigger/more power), add buffers, restructure logic (e.g. balance an AND-tree), or restructure arithmetic (carry-lookahead vs ripple). This is the area–power–timing trade-off.

Worked examples

Common mistakes

80/20 — the vital few

Flashcards

Connections

• RTL Design and the Synthesizable Subset
• Static Timing Analysis (STA)
• Standard Cell Libraries and .lib Timing Models
• Place and Route (Physical Design)
• Setup and Hold Time in Flip-Flops
• Clock Skew and Uncertainty
• HDL & Digital Design Flow

Concept Map

Hinglish (regional understanding)