Synthesis to gate-level netlist: Worked examples — Hardware deep dive

This deep dive is the "practice arena" for the synthesis setup-timing constraint from the parent note, Synthesis to gate-level netlist. We built the inequality there; here we drive it through every possible situation so no case can surprise you.

Before we begin, let us re-anchor every symbol so a reader who skipped the parent can still start at line one.

Definition The five quantities (all in nanoseconds)

Picture two boxes — call them FF1 (the launch flip-flop) and FF2 (the capture flip-flop) — with a cloud of logic gates between them. A clock line ticks both.

$T$ = the clock period — the time from one tick to the next tick. This is the whole budget.
$t_{c q}$ = clock-to-Q delay — after the tick, FF1 does not spit out its new value instantly; it takes $t_{c q}$ to appear at its output pin Q.
$t_{l o g i c}$ = combinational delay — the time the signal spends crawling through the gate cloud between FF1 and FF2. This is the only term synthesis directly controls (by choosing faster/slower cells).
$t_{s u}$ = setup time — FF2 demands the data sit still for $t_{s u}$ before the capturing tick, or it may store garbage. It effectively moves the deadline earlier.
$t_{u n c}$ = clock uncertainty — a safety cushion for jitter and skew: the tick may not land exactly where we planned.

The figure below is the picture behind every example on this page — keep glancing back at it.

Figure — Synthesis to gate-level netlist

How to read the figure: the blue box on the left is FF1 (launch) and the pink box on the right is FF2 (capture). The yellow arrow leaving FF1 is the clock-to-Q delay $t_{c q}$ — the head-start the data loses before it even sets off. The wavy chalk-white blob in the middle is the logic cloud the signal must cross ( $t_{l o g i c}$ ). The pink arrow entering FF2 marks the moment the setup window $t_{s u}$ begins, i.e. the deadline shifted earlier. Along the bottom is the clock waveform: the blue tick is the launch edge, the pink tick is the next edge, and the yellow double-arrow between them is the whole budget $T$ . Everything the data does — the yellow arrow, the crossing of the blob, and the pink window — must fit inside that yellow $T$ . That "must fit inside $T$ " is literally the inequality below.

Why an inequality and not an equation? Because we do not need the data to arrive exactly on time — we need it to arrive no later than the deadline. " $\leq$ " is the natural language of a deadline.

The scenario matrix

Every setup-timing question you can be asked falls into one of these case classes. Each row is a distinct "shape" of problem; the examples below each announce which cell(s) they hit.

#	Case class	What makes it distinct	Example
A	Positive slack (comfortably met)	answer $> 0$ , no fix	Ex 1
B	Exactly-zero slack (boundary)	answer $= 0$ , the knife-edge	Ex 2
C	Negative slack → fix (violation)	answer $< 0$ , then re-map	Ex 3
D	Degenerate: no logic ( $t_{l o g i c} = 0$ )	flop-to-flop, back-to-back	Ex 4
E	Solve for max clock frequency	rearrange for $T$ , invert to MHz	Ex 5
F	Solve for the unknown budget ( $t_{l o g i c}$ max)	rearrange for one term	Ex 6
G	Zero uncertainty vs. added skew	limiting value $t_{u n c} \to 0$ , then large	Ex 7
H	Word problem (real trade-off)	choose a cell mapping to pass	Ex 8
I	Exam twist: "bigger gate hurt"	upsizing raises $t_{c q}$ elsewhere	Ex 9

Together A–I cover: every sign of slack (+, 0, −), every degenerate input ( $t_{l o g i c} = 0$ , $t_{u n c} = 0$ ), the limiting direction (max frequency), an inverse solve, a word problem, and an exam trap.

Worked examples

Worked example Example 1 — Comfortable pass (Case A)

$T = 2.0$ , $t_{c q} = 0.20$ , $t_{l o g i c} = 1.30$ , $t_{s u} = 0.15$ , $t_{u n c} = 0.10$ ns. Does the path pass, and by how much?

Forecast: Add the four eaters and see if there's room in 2 ns. Guess the sign of slack before reading on.

Sum the delays. $0.20 + 1.30 + 0.15 + 0.10 = 1.75$ ns. Why this step? The inequality compares the total time the data experiences against $T$ ; that total is just the sum.
Subtract from the period. $slack = 2.0 - 1.75 = + 0.25$ ns. Why this step? Slack is defined as "budget minus what you spent."
Read the sign. $+ 0.25 > 0 \Rightarrow$ timing met, no fix. Why this step? Positive slack means the data arrived with time to spare.

Verify: Units all ns; $1.75 < 2.0$ so a positive result is expected. Spare fraction $= 0.25/2.0 = 12.5%$ headroom — plausible for a healthy path.

Worked example Example 2 — The knife-edge (Case B: exactly zero)

$T = 1.60$ , $t_{c q} = 0.25$ , $t_{l o g i c} = 1.10$ , $t_{s u} = 0.15$ , $t_{u n c} = 0.10$ ns. What is the slack?

Forecast: These numbers are engineered. Guess whether it clears or fails.

Sum. $0.25 + 1.10 + 0.15 + 0.10 = 1.60$ ns. Why this step? Same total-time reasoning as Ex 1.
Slack. $slack = 1.60 - 1.60 = 0.00$ ns. Why this step? The deadline is met precisely.
Interpret the boundary. Because the constraint is " $\leq T$ ", zero slack passes — but with no margin. Any tiny extra delay tips it negative. Why this step? This is exactly why $t_{u n c}$ exists: real chips need cushion, so engineers rarely ship at zero slack.

Verify: $1.60 = 1.60$ ; slack $= 0$ is the boundary between Case A and Case C. Sanity: if you nudged $t_{l o g i c}$ up by $0.01$ , slack would be $- 0.01$ — a violation.

Worked example Example 3 — Violation, then the fix (Case C)

$T = 2.0$ , $t_{c q} = 0.20$ , $t_{s u} = 0.15$ , $t_{u n c} = 0.10$ ns. A ripple adder gives $t_{l o g i c} = 2.00$ ns. Fix it.

Forecast: The adder alone already equals $T$ . Guess the sign, then guess whether swapping cells can save it.

Slack with the ripple adder. $2.0 - (0.20 + 2.00 + 0.15 + 0.10) = 2.0 - 2.45 = - 0.45$ ns. Why this step? Negative slack pinpoints the adder as too slow — the largest term.
Attack the only synthesis-controlled term, $t_{l o g i c}$ . Re-map the ripple adder to a carry-lookahead structure with $t_{l o g i c} = 1.40$ ns. Why this step? We cannot change $T$ (spec) or the flop's $t_{c q} / t_{s u}$ (fixed by the .lib cell); logic restructuring is the lever we own.
Recompute. $slack = 2.0 - (0.20 + 1.40 + 0.15 + 0.10) = 2.0 - 1.85 = + 0.15$ ns $✓$ . Why this step? Confirm the fix flipped the sign to positive.

Verify: $- 0.45$ then $+ 0.15$ ; the fix recovered $2.00 - 1.40 = 0.60$ ns, and $- 0.45 + 0.60 = + 0.15$ ✓. The trade-off: carry-lookahead costs more area/power — the classic timing↔area↔power balance.

Worked example Example 4 — Degenerate: flops back-to-back (Case D,

$t_{l o g i c} = 0$ ) $T = 0.50$ , $t_{c q} = 0.20$ , $t_{l o g i c} = 0$ (FF1's Q wires straight into FF2's D), $t_{s u} = 0.15$ , $t_{u n c} = 0.05$ ns. Pass?

Forecast: No gates at all — surely trivially fast? Careful, guess anyway.

Set $t_{l o g i c} = 0$ . The cloud is empty; the only delays are the flops and the cushion. Why this step? A direct Q→D connection is a real, common structure (a shift register); the formula still applies with $t_{l o g i c} = 0$ .
Slack. $0.50 - (0.20 + 0 + 0.15 + 0.05) = 0.50 - 0.40 = + 0.10$ ns. Why this step? Even with zero logic, $t_{c q} + t_{s u} + t_{u n c}$ still consumes budget — proving the flops themselves have overhead.
Interpret. Passes, but a very fast clock could still fail this: the flop overhead alone ( $0.40$ ns) sets a floor on $T$ . Why this step? This is the intuition behind Case E next.

Verify: $0.40 < 0.50$ ; $+ 0.10$ slack. Degenerate check: setting the logic to nothing did not make timing automatic — good, the model is honest.

Worked example Example 5 — Maximum clock frequency (Case E: limiting value)

Given $t_{c q} = 0.20$ , $t_{l o g i c} = 1.30$ , $t_{s u} = 0.15$ , $t_{u n c} = 0.05$ ns, what is the fastest clock (highest frequency) this path allows?

Forecast: Guess: is the answer around 500 MHz or 1 GHz?

Rearrange the inequality for $T$ . From $t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c} \leq T$ , the smallest legal $T$ is $T_{m i n} = t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c}$ . Why this step? The fastest clock is the shortest period, and the shortest legal period is exactly when slack $= 0$ .
Plug in. $T_{m i n} = 0.20 + 1.30 + 0.15 + 0.05 = 1.70$ ns. Why this step? This is the boundary of Case B applied as a design target.
Convert to frequency. $f_{m a x} = \frac{1}{T _{m i n}} = \frac{1}{1.70 ns} = \frac{1}{1.70 \times 1 0 ^{- 9} s} \approx 5.88 \times 1 0^{8} Hz \approx 588 MHz$ . Why this step? Frequency is the reciprocal of period; we invert seconds to hertz. We use reciprocal (not, say, a derivative) because frequency is by definition ticks-per-second $= 1/ T$ .

Verify: $1/1.70 = 0.5882 \dots$ ; times $1 0^{9}$ gives $588$ MHz. Sanity: a slower logic path would push $T_{m i n}$ up and $f_{m a x}$ down — correct direction.

Worked example Example 6 — Inverse solve: how slow may the logic be? (Case F)

$T = 1.25$ , $t_{c q} = 0.18$ , $t_{s u} = 0.12$ , $t_{u n c} = 0.10$ ns. What is the largest $t_{l o g i c}$ that still passes?

Forecast: Guess roughly how many ns are left for the gates.

Isolate $t_{l o g i c}$ . From $t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c} \leq T$ : $t_{l o g i c} \leq T - t_{c q} - t_{s u} - t_{u n c}$ . Why this step? We treat the unknown as the subject and move everything known to the other side — same algebra, different unknown.
Plug in. $t_{l o g i c, m a x} = 1.25 - 0.18 - 0.12 - 0.10 = 0.85$ ns. Why this step? This is the exact budget synthesis is allowed to spend on gates for this path.
Interpret. If the tool's chosen cells sum to more than $0.85$ ns, it must restructure or upsize. Why this step? This number is literally the target STA hands to optimization.

Verify: Back-substitute $t_{l o g i c} = 0.85$ : slack $= 1.25 - (0.18 + 0.85 + 0.12 + 0.10) = 1.25 - 1.25 = 0$ ✓ — exactly the boundary, as an "at most" answer should be.

Worked example Example 7 — Uncertainty: zero, then large (Case G: limiting inputs)

Path: $T = 2.0$ , $t_{c q} = 0.20$ , $t_{l o g i c} = 1.50$ , $t_{s u} = 0.15$ ns. Compare $t_{u n c} = 0$ (ideal clock) with $t_{u n c} = 0.30$ ns (real, skewed clock).

Forecast: Guess whether the ideal-clock result is misleadingly optimistic.

Ideal clock, $t_{u n c} = 0$ . $slack = 2.0 - (0.20 + 1.50 + 0.15 + 0) = 2.0 - 1.85 = + 0.15$ ns. Why this step? Removing the cushion shows the "paper" margin — useful to see how much cushion eats.
Real clock, $t_{u n c} = 0.30$ . $slack = 2.0 - (0.20 + 1.50 + 0.15 + 0.30) = 2.0 - 2.15 = - 0.15$ ns. Why this step? Adding realistic skew flips a "pass" into a violation — this is why STA never signs off on an ideal clock.
Interpret the swing. The slack moved by exactly $0.30$ ns — the whole uncertainty. Uncertainty enters linearly and subtracts directly from margin. Why this step? Shows there's no hidden nonlinearity; each ns of skew costs one ns of slack.

Verify: $+ 0.15$ vs $- 0.15$ ; difference $= 0.30 = t_{u n c}$ change ✓. Limiting sanity: as $t_{u n c} \to 0$ we recover the optimistic bound; as $t_{u n c}$ grows the path eventually always fails.

Worked example Example 8 — Word problem: pick a mapping to pass (Case H)

A 350 MHz design. The library offers a datapath in three flavors: ripple ( $t_{l o g i c} = 2.60$ ), skip ( $1.90$ ), or lookahead ( $1.40$ ) ns. Fixed: $t_{c q} = 0.22$ , $t_{s u} = 0.18$ , $t_{u n c} = 0.12$ ns. Which is the smallest/cheapest flavor that still meets timing?

Forecast: Guess: does the cheap ripple version survive at 350 MHz?

Find the period. $T = 1/ f = 1/ (350 \times 1 0^{6} Hz) = 2.857 ns$ (since period is reciprocal of frequency). Why this step? Constraints come as a clock frequency; the inequality needs $T$ .
Compute the logic budget (Case F reasoning): $t_{l o g i c, m a x} = T - t_{c q} - t_{s u} - t_{u n c} = 2.857 - 0.22 - 0.18 - 0.12 = 2.337$ ns. Why this step? Any flavor with $t_{l o g i c} \leq 2.337$ passes; we can now just compare.
Compare the three. Ripple $2.60 > 2.337$ → fails. Skip $1.90 \leq 2.337$ → passes. Lookahead $1.40$ → passes but is bigger/costlier than needed. Why this step? We want the cheapest passing option — that's skip (smallest area among passers).

Verify: Skip slack $= 2.857 - (0.22 + 1.90 + 0.18 + 0.12) = 2.857 - 2.42 = + 0.437$ ns $> 0$ ✓. Ripple total spend $= 0.22 + 2.60 + 0.18 + 0.12 = 3.12$ ns, which exceeds $T = 2.857$ , so ripple slack $= 2.857 - 3.12 = - 0.263$ ns $< 0$ → fails ✓. Choosing skip over lookahead saves area — the trade-off in action.

Worked example Example 9 — Exam twist: the "bigger gate" trap (Case I)

A path currently reads $slack = + 0.10$ ns. A student upsizes the final gate to chase margin: its own delay drops so $t_{l o g i c}$ falls by $0.20$ ns — but the bigger gate loads the flop's output, so the effective launch delay $t_{c q}$ rises by $0.15$ ns. Start values: $T = 1.5$ , $t_{c q} = 0.25$ , $t_{l o g i c} = 0.98$ , $t_{s u} = 0.12$ , $t_{u n c} = 0.05$ ns. Did the upsize help, and by how much?

Forecast: "Bigger is faster," right? Guess the new slack sign and whether the gain is the full $0.20$ ns.

Confirm the starting slack. $slack = 1.5 - (0.25 + 0.98 + 0.12 + 0.05) = 1.5 - 1.40 = + 0.10$ ns. Why this step? Establish the true baseline before changing anything.
Apply both effects. New $t_{l o g i c} = 0.98 - 0.20 = 0.78$ ; new $t_{c q} = 0.25 + 0.15 = 0.40$ . Why this step? Upsizing is not free: shrinking one gate's delay increases the load it presents, slowing the driver — a global effect, not a local win.
Recompute the slack. $slack = 1.5 - (0.40 + 0.78 + 0.12 + 0.05) = 1.5 - 1.35 = + 0.15$ ns. Why this step? Compare to the old $+ 0.10$ : the net gain is only $+ 0.05$ , not the naive $+ 0.20$ , because the $t_{c q}$ penalty ate most of it.
Interpret. The upsize did help — slack rose from $+ 0.10$ to $+ 0.15$ — but only by $0.05$ ns, a quarter of what the logic improvement suggested in isolation. Why this step? This is the punchline: local greed ≠ global gain (parent note's mistake #3). A tool that greedily upsizes every gate can even make timing worse when the $t_{c q}$ /load penalty exceeds the logic saving.

Verify: Old slack $+ 0.10$ , new $+ 0.15$ ; the logic improvement was $0.20$ but $t_{c q}$ cost $0.15$ , net $0.20 - 0.15 = 0.05$ , and $0.10 + 0.05 = 0.15$ ✓. Lesson: local greed ≠ global gain — exactly the parent note's mistake #3.

Recall Quick self-test on the matrix

Which case is "solve for $f_{m a x}$ "? ::: Case E — set slack to zero, take $T_{m i n}$ , invert to frequency. Zero slack: pass or fail? ::: Pass (the constraint is $\leq T$ ) but with no margin — Case B. Does $t_{l o g i c} = 0$ guarantee timing is met? ::: No — flop overhead $t_{c q} + t_{s u} + t_{u n c}$ still consumes budget (Case D). Why can upsizing a gate fail to help? ::: It raises the load on the driving stage, adding delay elsewhere (Case I).