Synthesis to gate-level netlist: Question bank — Hardware deep dive

Three words carry over from the parent note: RTL (register-transfer-level HDL — behavioral "what I want"), netlist (a structural list of real cells wired together), slack (spare time on a timing path). Everything below leans on those.

Definition Every symbol and acronym used on this page

Before any trap, here is the whole cast of characters, in plain words — nothing below assumes you looked elsewhere.

$T$ — the clock period: the time between two consecutive ticks of the clock, i.e. the budget one signal has to travel from one flip-flop to the next.
$t_{c q}$ — clock-to-Q delay: after the clock ticks, the launching flip-flop does not spit out its value instantly; $t_{c q}$ is that small startup delay.
$t_{l o g i c}$ — combinational logic delay: time for the signal to travel through the gates between the two flip-flops. This is the number synthesis actually controls.
$t_{s u}$ — setup time: the capturing flip-flop needs data held steady this long before its clock edge, or it stores garbage.
$t_{h}$ — hold time: the capturing flip-flop needs data held steady this long after its clock edge (used only in the hold edge cases below).
$t_{u n c}$ — clock uncertainty: a safety margin covering jitter and estimated clock skew.
GTECH — generic technology: the technology-independent Boolean network (abstract AND/OR/NOT graph) that synthesis builds before it knows any real gate.
SDC — Synopsys Design Constraints: the constraints file that states the clock period, input/output delays, area budget, etc.
STA — Static Timing Analysis: the check that measures every path's slack.

Figure — Synthesis to gate-level netlist

The figure above is the picture behind every timing trap: one clock period $T$ is a fixed box, and $t_{c q}$ , $t_{l o g i c}$ , $t_{s u}$ , $t_{u n c}$ are chunks that must all fit inside it. Whatever room is left over is the slack.

True or false — justify

TF: The gate-level netlist is written in a different language than the RTL.

False — it is still Verilog syntactically; the difference is it contains only instantiated cells, no always/if/+ behavior.

TF: Synthesis decides the physical position of each gate on the chip.

False — synthesis produces a logical netlist (which cells, how wired); placement & routing decides where they sit.

TF: If RTL simulates correctly, it is guaranteed to synthesize into working hardware.

False — RTL can hold non-synthesizable constructs (#delays, initial logic, unbounded loops) that simulate fine but have no hardware meaning; only the synthesizable subset maps to gates.

TF: Technology mapping happens before the generic (GTECH) network is built.

False — the order is elaborate → build GTECH → optimize GTECH → tech-map → post-map optimize; you optimize the abstract Boolean network before committing to real cells.

TF: A negative slack means the design is permanently broken.

False — it means this mapping misses timing; the tool (or you, via constraints/RTL/gate choices) resolves it. Treat it as a to-do, not a verdict.

TF: Positive slack always means "faster than needed", so more positive is always better.

Partly false — positive slack means timing is met, but large positive slack often signals over-sized, power-hungry gates you could shrink to save area/power.

TF: Upsizing a gate always shortens the timing path it sits on.

False — a bigger gate is a larger load on the gate driving it, slowing the previous stage; the net effect can be worse (see the slack figure and the .lib load-dependent delay models).

TF: The .lib technology library is optional if the constraints are given.

False — the library is the menu of real cells with real delay/area/power; without it the tool cannot know any actual timing number, so it is a required input.

TF: Synthesis can be run without any clock-period constraint and still optimize timing.

False (in intent) — with no clock/SDC the tool has no timing target, so it cannot meaningfully optimize for speed; it would just produce some legal mapping.

TF: The setup constraint

t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c} \leq T

counts the launching flop's output delay.

True —

t_{c q}

(clock-to-Q) is the launching flop not outputting instantly; it eats into the same period budget as the logic. See Setup and Hold Time in Flip-Flops.

Spot the error

Error: "Synthesis converts RTL directly to real library cells in one step."

It skips stages — behavior first becomes the technology-independent GTECH network, that network is optimized, then it is mapped to real cells, so Boolean optimization happens before vendor commitment.

Error: "There is only one optimization stage, and it runs after technology mapping."

There are really two rounds — a generic (GTECH-level) optimization of the abstract Boolean network before mapping, and a post-mapping optimization (sizing/buffering) after, because some gains only exist before real cells lock things in and others only exist once real delays are known.

Error: "Slack =

t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c} - T

Signs are flipped — slack

= T - (t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c})

; the way stated, positive would mean a violation, which is backwards.

Error: "

t_{u n c}

is the wire delay between the two flops."

No —

t_{u n c}

is clock uncertainty (jitter/skew estimate/margin); wire and gate delay live inside

t_{l o g i c}

Error: "To fix a violation, always restructure the RTL by hand."

Overstated — the tool first tries automatic fixes (upsize, buffer, restructure logic/arithmetic); manual RTL/constraint edits are a later resort.

Error: "Optimization is done greedily gate-by-gate for smallest local delay."

Wrong scope — it's a global balance of timing–area–power; a locally faster gate can hurt its driver, so local greed is not the goal.

Error: "A 2:1 conditional sel ? a : b becomes an AND-OR tree of three separate cells in the netlist."

It maps directly to a single MUX2X1 cell if the library has one — the whole point of tech-mapping is to cover logic with the best-fitting real cell.

Why questions

Why translate to a generic (technology-independent, GTECH) network before mapping to real cells?

So the Boolean network can be optimized once, abstractly, before locking in any specific vendor's gates — you don't want to re-optimize per library.

Why does synthesis need real cells (not GTECH) to check if timing is met?

Only real .lib cells carry actual delay/area/power numbers; the GTECH network is dimensionless, so slack can't be computed until mapping picks concrete cells.

Why is

t_{s u}

subtracted from the available time rather than added to the logic budget?

Because the capturing flop needs data steady before its edge, so the effective deadline moves earlier by

t_{s u}

, shrinking the window the logic may use.

Why does synthesis exist "mostly to hit timing" rather than just correctness?

Correct behavior is necessary but easy; the hard, tool-worthy job is choosing gates so every path fits inside one clock period

T

with positive slack.

Why is fixing a setup violation with a faster adder (carry-lookahead) a trade-off, not a free win?

The faster structure uses more gates, so it costs more area and power — you buy speed with silicon and energy.

Why can a design that met timing in synthesis still fail after place & route?

Synthesis estimates wire delay; real routing adds actual wire length and load, and STA on the placed design may reveal new violations.

Why does making logic faster never fix a hold violation the way it fixes a setup violation?

Hold is about data arriving too soon (racing past the capture edge); speeding logic up makes the race worse — hold is fixed by adding delay, not removing it.

Edge cases

Edge: What is the slack meaning when

t_{l o g i c} = 0

(two flops wired directly, no logic between)?

Setup slack

= T - (t_{c q} + t_{s u} + t_{u n c})

; there's still a constraint because clock-to-Q, setup, and uncertainty alone can consume the period at high clock speeds.

Edge: If two candidate mappings give exactly slack

= 0

, is timing met?

Yes — zero slack means data arrives exactly on the deadline, which technically passes, though it leaves no margin, so tools usually keep a small positive cushion.

Edge: Can a purely combinational block (no flip-flops) still have a setup constraint?

Not by itself — the setup equation needs a launch and capture flop; a combinational-only block's timing is constrained through the flops at its endpoints (input/output delays in the SDC).

Edge: What is a hold constraint, and how does it differ from setup?

Hold requires the new data to not arrive before

t_{h}

after the capture edge:

t_{c q} + t_{l o g i c} \geq t_{h} + t_{s k e w}

. Setup is about being fast enough (fits in

T

); hold is about being slow enough (doesn't race through the same edge).

Edge: Why is a hold violation independent of the clock period

T

Hold compares the earliest data arrival (

t_{c q} + t_{l o g i c}

) against the same edge's hold window;

T

(the gap to the next edge) never enters the hold inequality, so making the clock slower cannot fix a hold failure.

Edge: How does synthesis typically fix a hold violation?

By inserting buffers/delay cells on the too-fast path to slow it down — the opposite of the upsize-for-setup fix — which is why chasing setup and hold at once is a balancing act.

Edge: What does synthesis output for a case with an unhandled default, creating an implied latch?

It infers a latch cell to hold the old value — often unintended; it synthesizes but signals a latch inference warning, an RTL bug to fix.

Edge: If the library has no cell matching a needed generic function, what happens?

The tool composes it from smaller available cells (e.g. build a big gate from NANDs), possibly slower/larger, because it can only use what the .lib provides.

Edge: What happens to slack if you tighten

T

(raise the clock frequency) on an already-passing setup path?

Setup slack shrinks by the same amount

T

decreases; eventually it goes negative and the tool must re-optimize or the frequency is infeasible — but hold slack is untouched.

Recall One-line self-test

Say why "synthesis places gates" and "simulating RTL proves it synthesizes" are both false. Answer ::: Placement is a separate physical-design step; and RTL can contain non-synthesizable constructs that simulate but map to no hardware.