This page assumes you know nothing about digital chips. We build every word, every letter, every subscript the parent flow uses, one brick at a time. When you finish, re-read the parent and nothing will be unexplained.
Before any symbol, look at what a chip actually is.
A wire carries one of two values: 0 (low voltage) or 1 (high voltage). That is everything electrical we care about here — no in-between, just two states. We call one such value a bit.
A logic gate is a tiny machine that reads bits on its input wires and produces a bit on its output wire. Look at the red output in the figure: it becomes 1 only when both inputs are 1. That is an AND gate.
A clock is a special wire that goes 0,1,0,1,... forever at a steady beat, like a metronome. The moment it jumps from 0 to 1 is the rising edge — the heartbeat of the chip. Everything in this topic is measured against that beat.
Why the topic needs these: the whole output of synthesis is gates wired together, and the whole goal is to beat the clock. You cannot read the parent without these three.
Two kinds of circuit exist, and every symbol later depends on knowing which you're looking at.
Combinational logic (top, black): output depends only on the inputs right now. Give it the same inputs, you always get the same output, instantly (well — after a small delay we'll measure). No memory.
Sequential logic: it remembers. The memory element is the flip-flop (red box, bottom). A flip-flop copies its input to its output only on the clock's rising edge, then holds that value steady until the next edge.
Why the topic needs this: the entire setup-timing story is "data leaves FF1 on one tick, must reach FF2 before the next tick." No flip-flops, no timing.
You don't draw millions of gates by hand. You describe behaviour in a Hardware Description Language (HDL) like Verilog. When you describe it at the level of "what value each register holds each clock cycle, and what logic sits between registers," that style is called RTL — Register-Transfer Level.
Example RTL line from the parent:
always @(*) y = sel ? a : b;
Two pieces of this line need unpacking for a newcomer:
So the line reads: "whenever a, b, or sel changes, set y to a if sel is 1, otherwise b." That is a want, not a gate. Turning wants into gates is exactly what synthesis does — see RTL Design and the Synthesizable Subset for which wants are legal.
Synthesis cannot invent gates; it picks from a fixed catalogue supplied by the chip factory. That catalogue is the standard-cell library, delivered as a .lib file.
Think of it as a LEGO box where every brick has a price tag (area), a weight (power), and a speed rating (timing). But that "speed rating" and "weight" are each richer than a single number — this is where beginners oversimplify. Full detail lives in Standard Cell Libraries and .lib Timing Models; here is the honest picture:
Why the topic needs it: only real cells have real timing, so the tool must choose cells before it can know whether the clock is beaten (parent Stage 3).
A gate is not instant. When its input changes, its output changes a tiny moment later. That moment is the gate's delay, measured in nanoseconds (ns) — billionths of a second. (As Section 3 warned, that delay is really a rise/fall, load- and slew-dependent lookup; we use one symbol per path for readability.)
The parent uses several named delays. Here is every one, as a picture on the timeline above:
Why "ns" and not seconds? Chips run at billions of ticks per second, so T is a few ns; using seconds would be 0.000000002 — the small unit keeps numbers readable.
Now every symbol is defined, so we can read the parent's central inequality as a story, left to right along one clock period.
Follow the red data-arrow in the figure across ONE period T:
Tick. FF1's clock rises. The data isn't out yet — wait tcq.
Travel. The signal races through the gates: costs tlogic.
Arrive early. It must be steady tsubefore the next tick — so the deadline is pulled earlier by tsu.
Safety. Reserve tunc for clock jitter.
All four stacked together must fit inside the one period T:
Why an inequality and not an equation? We don't need the data to arrive exactly at the deadline — arriving early is fine (that's positive slack). We only forbid arriving late. "Late is forbidden, early is fine" is precisely ≤. The formal machinery that computes this over every path is Static Timing Analysis (STA).
The setup check catches logic that is too slow. But there is a mirror-image danger: logic that is too fast. Both FF1 and FF2 are clocked by the same edge. When that edge arrives, FF1 launches new data. If that new data races through the logic and reaches FF2 before FF2 has finished capturing the OLD data, the old snapshot is corrupted.
So FF2's input must stay stable for thold after the edge. The earliest the new data can arrive is tcq (FF1's fastest output) plus the shortest logic path tlogic,min. That earliest arrival must be no sooner than the hold window:
A gate-level netlist is just the answer synthesis writes down: a list of which library cells were chosen and exactly which wires connect them. It is a structural description — cells + connections — with no behaviour (if/+/always) left.
The netlist is logical (which cells, wired how), not physical (where they sit). Deciding physical position is a later step: Place and Route (Physical Design).
Read top-down: bits and clocks are the atoms; they build gates and flip-flops; those build RTL and the cell library; delays plus the clock period build the setup and hold tests; all of it feeds synthesis.
