Clock skew and jitter

WHAT are we talking about?

The key distinction (memorize this):

	Skew	Jitter
Nature	Spatial (FF-to-FF)	Temporal (edge-to-edge)
Deterministic?	Yes (fixed offset)	No (random)
Root cause	Unequal clock paths	Oscillator/supply noise

WHY does it matter? (First-principles timing)

A flip-flop needs data stable in a window around the clock edge:

Setup time $t_{su}$ : data must arrive before the edge.
Hold time $t_{h}$ : data must stay stable after the edge.

Consider launch FF1 → combinational logic → capture FF2, clock period $T$ .

Deriving the SETUP constraint (with skew)

FF1 sees the edge at $t=0$ . FF2 sees the next edge nominally at $t=T$ , but skewed by $t_{skew}$ , so FF2's capturing edge is at $T + t_{skew}$ .

Data is valid at FF2's D input at time: $t_{data} = t_{cq} + t_{logic}$

Requirement: data settled by setup window: $t_{cq} + t_{logic} + t_{su} \le T + t_{skew}$

Now add jitter — it can push the capture edge earlier by $t_{jitter}$ in the worst case (edge arrives sooner, less time available): $\boxed{t_{cq} + t_{logic} + t_{su} + t_{jitter} \le T + t_{skew}}$

Deriving the HOLD constraint (with skew)

Hold is about the same edge causing a race: the new data launched by FF1 at $t=0$ must NOT arrive at FF2 too fast and corrupt what FF2 is trying to capture on its own edge.

FF2's capturing edge is at $t_{skew}$ (same edge, skewed). New data arrives at FF2 at $t_{cq} + t_{logic,min}$ . It must arrive after the hold window closes: $t_{cq} + t_{logic,min} \ge t_{skew} + t_{h}$

Add jitter (edge can arrive later, worsening hold by $t_{jitter}$ ): $\boxed{t_{cq} + t_{logic,min} \ge t_{skew} + t_{h} + t_{jitter}}$

HOW to reason about the sign of skew

Worked Examples

Common Mistakes

Flashcards

Define clock skew.

Spatial, deterministic difference in clock-edge arrival time between two flip-flops from the same clock, due to unequal clock-tree paths.

Define clock jitter.

Temporal, random cycle-to-cycle variation of a clock edge from its ideal position, due to oscillator/PLL/supply noise.

Setup constraint with skew and jitter?

t_{cq}+t_{logic,max}+t_{su}+t_{jitter} \le T+t_{skew}

Hold constraint with skew and jitter?

t_{cq}+t_{logic,min} \ge t_{skew}+t_h+t_{jitter}

Why can't you fix a hold violation by lowering clock frequency?

The hold inequality contains no period

T

; it's an edge-vs-edge race on the same cycle, independent of

T

Does positive skew help or hurt setup?

Helps — the late capture edge gives data more time.

Does positive skew help or hurt hold?

Hurts — late capture edge lets fast new data violate the hold window.

Does jitter ever help timing?

No — being random, worst-case jitter always reduces margin for both setup and hold.

f_{max}

formula with uncertainty?

f_{max}=1/(t_{cq}+t_{logic,max}+t_{su}+t_{jitter}-t_{skew})

How to fix a hold violation?

Add delay/buffers to the data path (increase

t_{logic,min}

) or reduce clock skew.

Recall Feynman: explain to a 12-year-old

Imagine a relay race where a whistle tells everyone to run. Ideally everyone hears the whistle at the exact same instant. Skew is when the whistle's echo reaches some runners a little later because they stand farther — always the same delay. Jitter is when the timekeeper's hand shakes, so the whistle blows a tiny bit early or late each time — random. If runners start at slightly wrong times, some hand off the baton too soon (hold problem) or the next runner isn't ready yet (setup problem). Engineers leave extra time so nobody messes up the handoff.

Connections

Setup and Hold Time — the timing windows skew/jitter erode.
Flip-Flops — the storage elements being clocked.
Clock Distribution Network / Clock Tree — physical source of skew.
Phase Locked Loop (PLL) — main source of jitter.
Maximum Clock Frequency — directly reduced by jitter and negative skew.
Static Timing Analysis — where these constraints are checked.
Metastability — what happens when setup/hold are violated.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, ek clock ka kaam hai poore chip me ek saath "tick" bhejna — jaise ek dum sabko ek hi second me signal mile. Lekin real hardware me wires ki length alag hoti hai aur buffers me delay hota hai, isliye ek hi edge do alag flip-flops tak thodi alag time par pahunchta hai. Yeh spatial, fixed difference hi clock skew hai. Dusri taraf, jo oscillator/PLL clock banata hai wo bilkul perfect nahi hota — supply noise aur thermal noise ki wajah se har tick thoda early ya late aa jaata hai. Yeh random, cycle-to-cycle wobble jitter hai. Trick yaad rakho: Skew = Spatial & Steady, Jitter = Just Jumpy.

Ab yeh matter kyun karta hai? Flip-flop ko data chahiye setup time pehle stable, aur hold time tak stable. Setup constraint banta hai: $t_{cq}+t_{logic}+t_{su}+t_{jitter} \le T+t_{skew}$ . Yahan positive skew (capture clock late aata hai) tumhe extra time deta hai — helpful. Lekin jitter hamesha bura hai kyunki worst case me edge jaldi aa jaata hai. Isliye jitter ko period me pad karna padta hai.

Hold ka case ulta hai. Hold violation tab hota hai jab naya data FF2 par bahut jaldi pahunch jaata hai aur purana data corrupt kar deta hai: $t_{cq}+t_{logic,min} \ge t_{skew}+t_h+t_{jitter}$ . Notice karo — is equation me $T$ hai hi nahi! Matlab clock slow karke hold problem kabhi fix nahi hoti. Positive skew yahan dushman hai. Fix karne ka tareeka: data path me buffers/delay daalo, ya skew kam karo. Exam me bas sign yaad rakho: Setup Smiles with positive skew, Hold Howls.

WHAT are we talking about?

WHY does it matter? (First-principles timing)

Deriving the SETUP constraint (with skew)

Deriving the HOLD constraint (with skew)

HOW to reason about the sign of skew

Worked Examples

Common Mistakes

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Sequential Circuits

Connections