Clock skew and jitter: Worked examples — Hardware deep dive

Before anything, let us re-anchor every symbol this page uses so no notation appears unexplained.

Definition The quantities (in plain words + picture)

Look at the picture below. A signal is born inside a launch flip-flop, walks through logic, and must arrive calm at a capture flip-flop before that flip-flop's clock edge grabs it.

$t_{c q}$ — clock-to-Q: after the launch flip-flop hears its tick, how long until its output $Q$ actually changes. (The "reaction time" of the launch flop.) In s01 it is the coral arrow leaving FF1 (the lavender box).
$t_{l o g i c}$ — travel time through the combinational logic (the butter-coloured cloud in s01) between the two flops. Because different routes have different lengths, we split it into two named versions:
- $t_{l o g i c, ma x}$ — the slowest path (longest delay). Setup worries about this: the last, laziest bit must still make it in time.
- $t_{l o g i c, min}$ — the fastest path (shortest delay). Hold worries about this: the quickest bit must not arrive too early and overtake the edge.
$t_{s u}$ — setup time: the data must be still and correct for this long before the capture edge (the mint box FF2 in s01).
$t_{h}$ — hold time: the data must stay still for this long after the capture edge.
$t_{s k e w} = t_{c l k \to F F 2} - t_{c l k \to F F 1}$ — how much later the capture flop hears the tick than the launch flop. It is the coral double-arrow along the clock line in s01. Positive = capture is late; negative = capture is early.
$t_{j i tt er}$ — random wobble of any edge (the small lavender double-arrow on FF2's edge in s01); worst case it always steals margin.
$T$ — the clock period: the ideal time from one tick to the next (the slate double-arrow across the top of s01), the "one whole cycle" the setup race is run over.
$f$ (and its ceiling $f_{ma x}$ ) — the clock frequency, simply how many ticks per second: $f = 1/ T$ . When we push $T$ to its smallest legal value $T_{min}$ we get the highest legal frequency $f_{ma x} = 1/ T_{min}$ .
$Δ$ — an added data-path delay (extra buffers we deliberately insert into the logic path). It appears only when we repair a hold violation (Ex 6): it lengthens $t_{l o g i c, min}$ so fast data can no longer overtake the edge.

Everything from here on refers back to this picture — when a step says "the coral arrow" or "the mint capture flop", it means s01. Keep it in view.

The scenario matrix

Every problem this topic can pose is one cell below. The examples that follow are tagged with the cell(s) they cover.

#	Cell (the scenario class)	Which constraint	Covered by
A	Positive skew (capture late)	Setup — helps	Ex 1
B	Negative skew (capture early)	Setup — hurts	Ex 2
C	Zero skew, jitter only	Setup baseline	Ex 3
D	Positive skew	Hold — hurts, still safe	Ex 4
E	Positive skew	Hold — violation	Ex 5
F	Fixing a hold violation (add data delay $Δ$ )	Hold repair	Ex 6
G	Limiting / degenerate: skew → very large; $t_{l o g i c, min} = 0$	Both edges	Ex 7
H	Real-world word problem (clock tree buffer counting)	Skew from paths	Ex 8
I	Exam twist: given $f$ , solve for the max allowed skew	Setup rearranged	Ex 9
J	Negative skew HELPS hold (capture early)	Hold — helps	Ex 10

Notice every sign of skew (—, 0, +), presence/absence of jitter, both constraints, both hold directions, a violation, a fix, a degenerate limit, a word problem, and an inverse-solve all appear. That is "every scenario".

Worked Examples

Worked example Example 1 — Cell A: positive skew HELPS setup

$t_{c q} = 0.3$ ns, $t_{l o g i c, ma x} = 2.0$ ns, $t_{s u} = 0.2$ ns, $t_{j i tt er} = 0.05$ ns, $t_{s k e w} = + 0.1$ ns. Find $T_{min}$ and $f_{ma x}$ .

Forecast: guess — will positive skew make $T_{min}$ bigger or smaller? (Answer at the end.)

Rearrange the setup inequality to isolate $T$ : $T \geq t_{c q} + t_{l o g i c, ma x} + t_{s u} + t_{j i tt er} - t_{s k e w}$ . Why this step? We want the smallest legal period, so we push everything to the right and set equality. In s01 this is the coral arrows (data) racing the slate top arrow ( $T$ ) plus the coral skew arrow.
Plug in: $T_{min} = 0.3 + 2.0 + 0.2 + 0.05 - 0.1 = 2.45$ ns. Why this step? Jitter is added (it steals time), skew is subtracted (late capture edge donates time).
$f_{ma x} = 1/ T_{min} = 1/2.45 ns \approx 408.16$ MHz. Why this step? Frequency is the reciprocal of period ( $f = 1/ T$ ); ns → GHz means $1/2.45 = 0.408$ GHz.

Verify: units — ns cancel to give GHz; $0.408 GHz = 408$ MHz. Sanity: skew subtracted, so $T_{min}$ is smaller than without it — positive skew helps setup. ✓

Worked example Example 2 — Cell B: NEGATIVE skew HURTS setup

Same numbers as Ex 1 but the capture flop is now early: $t_{s k e w} = - 0.1$ ns.

Forecast: with the capture edge arriving early, is there more or less time for data?

Same formula: $T_{min} = t_{c q} + t_{l o g i c, ma x} + t_{s u} + t_{j i tt er} - t_{s k e w}$ . Why? The formula never changed; only the sign of the number does the work.
Substitute $t_{s k e w} = - 0.1$ : $T_{min} = 0.3 + 2.0 + 0.2 + 0.05 - (- 0.1) = 2.65$ ns. Why? Subtracting a negative adds — a negative skew makes the required period longer.
$f_{ma x} = 1/2.65 ns \approx 377.36$ MHz. Why this step? We convert the period ceiling into the frequency ceiling with $f_{ma x} = 1/ T_{min}$ , the same reciprocal relation from the definitions.

Verify: $2.65 > 2.45$ , so negative skew hurts setup (lower $f_{ma x}$ ) — exactly opposite of Ex 1. This confirms the parent's rule "positive skew borrows time". ✓

Worked example Example 3 — Cell C: zero skew, jitter-only baseline

$t_{c q} = 0.3$ , $t_{l o g i c, ma x} = 2.0$ , $t_{s u} = 0.2$ (ns), $t_{s k e w} = 0$ . Compare $T_{min}$ with $t_{j i tt er} = 0.05$ ns vs without jitter.

Forecast: how many ps of frequency does 50 ps of jitter cost you?

No jitter: $T_{min} = 0.3 + 2.0 + 0.2 = 2.5$ ns → $f = 400$ MHz. Why? With skew=0 and jitter=0 we see the "textbook" flip-flop equation.
With jitter: $T_{min} = 2.5 + 0.05 = 2.55$ ns → $f = 1/2.55 \approx 392.16$ MHz. Why? Jitter, being random, always adds to the required period — you cannot bank on it helping.
Cost of jitter $= 400 - 392.16 \approx 7.84$ MHz. Why this step? Subtracting the two frequency ceilings ( $f_{ma x}$ without minus with jitter) measures the concrete speed penalty jitter imposes, which is what a designer actually cares about.

Verify: period grew by exactly $t_{j i tt er} = 0.05$ ns; frequency dropped a little — a small jitter costs a modest frequency slice. ✓

Worked example Example 4 — Cell D: positive skew, hold still SAFE

$t_{c q} = 0.3$ , $t_{l o g i c, min} = 0.15$ , $t_{h} = 0.25$ , $t_{s k e w} = + 0.1$ , $t_{j i tt er} = 0.05$ (ns). Is hold safe?

Forecast: the new fast data must not beat the (late) capture edge + hold window. Guess safe or violated.

Left side (how fast new data can arrive): $LHS = t_{c q} + t_{l o g i c, min} = 0.3 + 0.15 = 0.45$ ns. Why? This is the earliest the freshly-launched data can reach FF2 (fastest logic path in s01's butter cloud).
Right side (deadline it must not beat): $RHS = t_{s k e w} + t_{h} + t_{j i tt er} = 0.1 + 0.25 + 0.05 = 0.40$ ns. Why? The capture edge is late by $t_{s k e w}$ , plus we must clear the hold window, plus worst-case jitter.
Compare with the sign convention above: hold margin $= LHS - RHS = 0.45 - 0.40 = + 0.05$ ns $\geq 0$ → hold satisfied. Why this step? Hold passes exactly when margin (LHS − RHS) is non-negative.

Verify: margin $= + 0.05$ ns $> 0$ . Safe, with $0.05$ ns spare. Note $T$ never appeared — hold is edge-vs-edge on one cycle. ✓

Worked example Example 5 — Cell E: too much positive skew BREAKS hold

Same as Ex 4 but the clock tree drifts: $t_{s k e w} = + 0.3$ ns.

Forecast: we did nothing to the data path, only made the capture edge later. Safe or violation?

LHS unchanged: $0.3 + 0.15 = 0.45$ ns. Why? Skew lives on the clock (the slate line in s01), not the data path — LHS cannot change.
RHS: $0.3 + 0.25 + 0.05 = 0.60$ ns. Why? Bigger positive skew = capture edge even later = new data has even more chance to overrun the hold window.
Hold margin $= LHS - RHS = 0.45 - 0.60 = - 0.15$ ns $< 0$ → HOLD VIOLATION. Why this step? A negative margin means the fast data overruns the hold window by that much.

Verify: margin $= - 0.15$ ns $< 0$ → fails, short by $0.15$ ns. This is the parent's warning: aggressive positive skew (useful skew) risks hold. ✓

Worked example Example 6 — Cell F: FIX the hold violation from Ex 5

Given Ex 5 fails by $0.15$ ns, how much extra data-path delay $Δ$ (buffers, as defined in the quantities list above) makes it just safe? And why not simply slow the clock?

Forecast: guess whether the fix touches the clock period or the data path.

New hold condition with $Δ$ added to the fast path: $t_{c q} + (t_{l o g i c, min} + Δ) \geq t_{s k e w} + t_{h} + t_{j i tt er}$ , i.e. $0.45 + Δ \geq 0.60$ . Why? $Δ$ is the extra buffer delay we insert into the butter logic cloud of s01; it delays the fast data so it can no longer overtake the same edge.
Solve: $Δ \geq 0.60 - 0.45 = 0.15$ ns. Choose $Δ = 0.15$ ns. Why? Exactly closing the $0.15$ ns gap restores the hold margin to $0$ ; a touch more gives positive margin.
Confirm the clock-period trick is useless: hold has no $T$ , so raising $T$ (slower clock — the top slate arrow in s01) leaves $0.45$ vs $0.60$ untouched. Why this step? This is the single most-tested misconception — you must add data delay, not slow the clock.

Verify: with $Δ = 0.15$ : LHS $= 0.45 + 0.15 = 0.60 =$ RHS → margin $= 0$ , just legal. Slowing the clock changes neither side. ✓

Worked example Example 7 — Cell G: limiting / degenerate case

Push it to extremes: $t_{l o g i c, min} = 0$ (a direct wire, no logic between flops) and let skew grow. With $t_{c q} = 0.3$ , $t_{h} = 0.25$ , $t_{j i tt er} = 0.05$ , find the largest positive skew the hold constraint can tolerate.

Forecast: with no logic delay, how much late-capture (skew) can hold survive?

Hold with $t_{l o g i c, min} = 0$ : $t_{c q} + 0 \geq t_{s k e w} + t_{h} + t_{j i tt er}$ → $0.3 \geq t_{s k e w} + 0.30$ . Why? We probe the worst (fastest) data path — a wire — where hold is most fragile.
Solve for the boundary: $t_{s k e w} \leq 0.3 - 0.30 = 0.0$ ns. Why? Any positive skew at all would break hold here, since the fast path barely covers the hold window.
Interpret the limit: as $t_{s k e w} \to$ any $> 0$ , the hold margin $\to$ negative — zero skew is the ceiling for a logic-free direct connection. Why this step? Testing the boundary value plus a nudge past it proves the ceiling is exact, not approximate — the standard way to confirm a limiting case.

Verify: at $t_{s k e w} = 0$ : LHS $0.3$ , RHS $0.30$ , margin $= 0$ (borderline). At $t_{s k e w} = 0.01$ : margin $- 0.01 < 0$ → fails. Degenerate case confirmed. ✓

Worked example Example 8 — Cell H: real-world word problem (build skew from the clock tree)

The clock reaches FF1 through 3 buffers, and FF2 through 5 buffers, each buffer $= 40$ ps, plus FF2 sits on a longer wire adding $30$ ps. Compute $t_{s k e w}$ , then check setup for a target period $T = 2.5$ ns with $t_{c q} = 0.3$ , $t_{l o g i c, ma x} = 2.0$ , $t_{s u} = 0.2$ , $t_{j i tt er} = 0.05$ (ns).

Forecast: more buffers to FF2 → is skew positive (capture late) or negative?

Path to FF1: $3 \times 40 = 120$ ps $= 0.12$ ns. Path to FF2: $5 \times 40 + 30 = 230$ ps $= 0.23$ ns. Why? Skew is a difference of physical path delays along the clock tree (the slate line feeding both boxes in s01) — count what each edge travels through.
$t_{s k e w} = t_{c l k \to F F 2} - t_{c l k \to F F 1} = 0.23 - 0.12 = 0.11$ ns (positive → capture late). Why? Matches the definition; FF2's longer tree means it hears the tick later.
Setup slack $= (T + t_{s k e w}) - (t_{c q} + t_{l o g i c, ma x} + t_{s u} + t_{j i tt er})$ : RHS $= 2.5 + 0.11 = 2.61$ , LHS $= 0.3 + 2.0 + 0.2 + 0.05 = 2.55$ . Why? We plug the derived skew into the real setup budget.
Setup slack $= 2.61 - 2.55 = + 0.06$ ns $\geq 0$ → setup passes with $0.06$ ns spare. Why this step? Setup holds exactly when slack (RHS − LHS) is non-negative; that number is what a timing tool reports.

Verify: skew $= 0.11$ ns; setup slack $= + 0.06$ ns $> 0$ . Positive skew rescued a period that would fail at zero skew ( $2.55 > 2.50$ ). ✓

Worked example Example 9 — Cell I: exam twist (solve for max allowed skew)

A design must run at $f = 500$ MHz ( $T = 2.0$ ns) with $t_{c q} = 0.3$ , $t_{l o g i c, ma x} = 1.5$ , $t_{s u} = 0.2$ , $t_{j i tt er} = 0.05$ (ns). What is the minimum positive skew the clock tree must provide for setup to pass?

Forecast: the budget is tight — do we need skew to help, and how much?

Setup: $t_{c q} + t_{l o g i c, ma x} + t_{s u} + t_{j i tt er} \leq T + t_{s k e w}$ → $2.05 \leq 2.0 + t_{s k e w}$ . Why? LHS $= 0.3 + 1.5 + 0.2 + 0.05 = 2.05$ ns; we solve the inequality for $t_{s k e w}$ .
Rearrange: $t_{s k e w} \geq 2.05 - 2.0 = 0.05$ ns. Why? We need at least $0.05$ ns of late capture edge to borrow the missing time (setup slack $= 0$ at that value).
Caution flag: this positive skew now eats hold margin — designer must recheck hold (Cell E lesson). Why this step? Every setup fix via skew is a hold risk — always the paired check.

Verify: at $t_{s k e w} = 0.05$ : RHS $= 2.0 + 0.05 = 2.05 =$ LHS → setup slack $= 0$ , exactly met. Any less fails. ✓

Worked example Example 10 — Cell J: NEGATIVE skew HELPS hold

A hold path was failing; the designer routes the clock so the capture flop is early: $t_{s k e w} = - 0.1$ ns. With $t_{c q} = 0.3$ , $t_{l o g i c, min} = 0.15$ , $t_{h} = 0.25$ , $t_{j i tt er} = 0.05$ (ns), is hold now safe?

Forecast: an early capture edge closes its hold window sooner — does the fast data now clear it?

LHS (earliest data arrival): $t_{c q} + t_{l o g i c, min} = 0.3 + 0.15 = 0.45$ ns. Why? Same fastest-path arrival as before; the data path (the coral arrows through the butter cloud in s01) is unchanged.
RHS (deadline): $t_{s k e w} + t_{h} + t_{j i tt er} = - 0.1 + 0.25 + 0.05 = 0.20$ ns. Why this step? Negative skew means the capture edge is early, so the hold window closes sooner — the deadline the data must beat drops.
Hold margin $= LHS - RHS = 0.45 - 0.20 = + 0.25$ ns $\geq 0$ → hold satisfied with $0.25$ ns spare. Why this step? A large positive margin means the fast data clears the (now earlier) hold window comfortably — the mirror image of Ex 5.

Verify: margin $= + 0.25$ ns $> 0$ , far safer than the $+ 0.1$ ns skew case (Ex 4 margin $+ 0.05$ ). Confirms: negative skew helps hold exactly as much as it hurts setup. ✓

Common Mistakes (scenario-specific)

Recall Self-test across the matrix

Which cell has no $T$ in its inequality? ::: Every hold cell (D, E, F, G, J) — hold is edge-vs-edge on one cycle. In Ex 2, why does the answer grow versus Ex 1? ::: Skew is negative, and subtracting a negative adds to $T_{min}$ . In Ex 7, what is the largest tolerable positive skew for a logic-free path? ::: $0$ ns — any positive skew breaks hold when $t_{l o g i c, min} = 0$ here. In Ex 9, minimum skew to hit 500 MHz? ::: $0.05$ ns of positive skew. In Ex 10, does negative skew help or hurt hold? ::: Helps — the early capture edge closes the hold window sooner, so fast data clears it easily. What is the sign convention for "safe"? ::: Setup slack = RHS − LHS ≥ 0; hold margin = LHS − RHS ≥ 0. Positive means spare time, negative means violation.

Connections

Setup and Hold Time — the windows every example races against.
Maximum Clock Frequency — Ex 1–3, 8, 9 compute exactly this.
Static Timing Analysis — the tool that runs all ten cells automatically.
Clock Distribution Network — Ex 8's buffer counting lives here.
Phase Locked Loop (PLL) — source of the $t_{j i tt er}$ term.
Flip-Flops — the launch/capture elements.
Metastability — what a violated cell (Ex 5) can cause.