Clock skew and jitter: Foundations — Hardware deep dive

Before you can read a line like $t_{c q} + t_{l o g i c} + t_{s u} + t_{j i tt er} \leq T + t_{s k e w}$ , you must be able to see every one of those symbols on a timeline. That is the whole job of this page. We define each piece, draw it, and say why the topic cannot live without it.

0. The stage: a clock is a repeating up-and-down signal

Look at the figure. The blue line is the clock. The vertical orange marks are the rising edges — the only moments anything happens. The gray bracket marks one full period $T$ — literally the span between one tick and the next. Everything in this whole topic is about when exactly those orange marks land.

The frequency $f$ is just how many ticks happen per second, and it is the flip of the period:

We use the reciprocal (one-over) because "how long each tick lasts" and "how many ticks per second" are two views of the same thing: make each tick shorter and you fit more per second. That is exactly the trade the parent note's max-frequency result is about.

1. The two flip-flops and the path between them

Everything in this topic involves a launch flip-flop that sends data and a capture flip-flop that receives it, with some logic in between.

Follow the arrows: the clock (blue) fans out to both flip-flops. FF1's Q output runs through a cloud of combinational logic (gray) — AND/OR gates that compute something — and lands on FF2's D input. FF2 grabs that value on its own next edge.

2. The delay symbols — where every $t$ comes from

Now we name each chunk of time. These are the letters that fill the parent's inequalities. Read them left-to-right as a signal's journey.

We must track both the slowest and the fastest path, because a late signal can miss the next tick (a setup problem) while an early signal can crash into the current tick (a hold problem). One number cannot describe both dangers — that is why the topic always carries a "max" and a "min".

The green band is the setup interval $t_{s u}$ (to the left of the edge) and the red band is the hold interval $t_{h}$ (to the right of the edge). They are two separate windows with opposite directions. If the data (blue) wiggles inside either band, the flip-flop can go into metastability — an undecided, dangerous state. The parent's inequalities exist purely to keep the data out of these bands.

3. Now the two stars of the topic: skew and jitter

We finally have enough pictures to define the two words the whole note is named after.

Definition Clock skew

$t_{s k e w}$ and its sign convention The clock wire to FF2 may be longer or more loaded than the wire to FF1, so the same edge reaches FF2 a bit later. That fixed offset is skew: $t_{s k e w} = t_{c l k \to F F 2} - t_{c l k \to F F 1}$ Sign convention (memorize it):

$t_{s k e w} > 0$ (positive skew): the capture clock (FF2) arrives later than the launch clock (FF1). FF2's next edge effectively lands at $T + t_{s k e w}$ , i.e. later — more time for setup, less safety for hold.
$t_{s k e w} < 0$ (negative skew): the capture clock arrives earlier than the launch clock. Its next edge lands at $T - ∣ t_{s k e w} ∣$ , i.e. sooner — less time for setup, more safety for hold.
$t_{s k e w} = 0$ : both flip-flops hear the edge together (the ideal). It is spatial (between two places) and deterministic (the same every cycle) because wire lengths don't change. Its physical home is the clock tree.

Top row: the ideal ticks (evenly spaced). Middle: skew shifts FF2's whole comb of ticks sideways by a fixed amount (blue vs orange, always the same gap). Bottom: jitter leaves each single edge in a random fuzzy zone (red bands) around where it should be. This single picture is the difference the entire topic hinges on.

4. The tools the topic borrows — and why each one

5. Putting the symbols on one timeline — BOTH rules

Now we place every letter, and derive both the setup and the hold rule, so nothing is left off the timeline.

5a. The SETUP story (uses $t_{l o g i c, ma x}$ , races the NEXT edge)

Read this as a signal's journey against FF2's next tick:

Tick fires at FF1 (time $0$ ).
Wait $t_{c q}$ — Q appears.
Travel $t_{l o g i c, ma x}$ (slowest path) — reach FF2's D.
Must be steady $t_{s u}$ before FF2's next tick, which sits at $T$ , nudged by $+ t_{s k e w}$ , and can be pulled early by $t_{j i tt er}$ .

Data needs $t_{c q} + t_{l o g i c, ma x} + t_{s u}$ ; the deadline is $T + t_{s k e w} - t_{j i tt er}$ . Requiring "needs $\leq$ available": $t_{c q} + t_{l o g i c, ma x} + t_{s u} \leq T + t_{s k e w} - t_{j i tt er}$ Move jitter left (pure algebra) to match the parent's boxed form: $time the data needs t_{c q} + t_{l o g i c, ma x} + t_{s u} + t_{j i tt er} \leq time available T + t_{s k e w}$

5b. The HOLD story (uses $t_{l o g i c, min}$ , races the SAME edge)

Hold is a different race, on the same tick. The new data FF1 launches at time $0$ must not reach FF2 so fast that it overwrites what FF2 is still trying to capture on its copy of that same edge:

Tick fires at FF1 (time $0$ ).
New data reaches FF2's D after only $t_{c q} + t_{l o g i c, min}$ (the fastest path — the danger).
FF2's own capturing edge lands at $t_{s k e w}$ (same edge, just skewed), and jitter can push it later by $t_{j i tt er}$ , extending the hold window's reach.
The new data must arrive after the hold window closes.

Data arrives at $t_{c q} + t_{l o g i c, min}$ ; the hold window closes at $t_{s k e w} + t_{h} + t_{j i tt er}$ . Requiring "arrives after the window": $t_{c q} + t_{l o g i c, min} \geq t_{s k e w} + t_{h} + t_{j i tt er}$

Prerequisite map

Equipment checklist

What does a rising edge mean and why do flip-flops only care about it?

The instant the clock jumps LOW→HIGH; flip-flops sample their input only at that "tick", so nothing happens between edges.

What is the clock period

T

and what does it represent physically?

The time between two consecutive rising edges — the timing budget every delay must fit inside.

How are frequency

f

and period

T

related, and why the reciprocal?

f = 1/ T

; shorter tick means more ticks per second, and one-over reverses small and large.

What is

t_{c q}

Clock-to-Q delay — the small time after an edge before a flip-flop's output Q shows the new value.

Why do we track both

t_{l o g i c, ma x}

and

t_{l o g i c, min}

Slowest path threatens setup (arrives too late); fastest path threatens hold (arrives too early) — one number can't guard both.

What is the difference between setup time and hold time?

Setup = data steady before the edge (don't be late); hold = data steady after the edge (don't be early).

Define clock skew and its sign convention.

t_{s k e w} = t_{c l k \to F F 2} - t_{c l k \to F F 1}

; positive = capture clock late (helps setup, hurts hold), negative = capture clock early (hurts setup, helps hold), zero = ideal.

What quantity does

t_{j i tt er}

measure and how is it used worst-case?

Peak-to-peak edge displacement (worst-case wander of one edge); always subtracts margin, so it hurts both setup and hold.

Write the setup constraint with skew and jitter and say which path it uses.

t_{c q} + t_{l o g i c, ma x} + t_{s u} + t_{j i tt er} \leq T + t_{s k e w}

; uses the slowest (max) logic path and races the next edge.

Write the hold constraint with skew and jitter and say which path it uses.

t_{c q} + t_{l o g i c, min} \geq t_{s k e w} + t_{h} + t_{j i tt er}

; uses the fastest (min) logic path and races the same edge — no

T

Why are timing rules written as inequalities, not equalities?

We need data no later (setup) or no earlier (hold) than a deadline; "in time" is a range, which

\leq

\geq

captures.

Where do skew and jitter physically come from?

Skew from the clock distribution network (wire lengths/loads); jitter from the PLL and power-supply/thermal noise.

Connections

Setup and Hold Time — the windows these delays must respect.
Flip-Flops — the edge-triggered memory cells.
Clock Distribution Network — physical home of skew.
Phase Locked Loop (PLL) — source of jitter.
Maximum Clock Frequency — built from $T_{min}$ .
Static Timing Analysis — the worst-case-corner mindset.
Metastability — what a violated window causes.
3.4.15 Clock skew and jitter (Hinglish) — same idea in Hinglish.