Exercises — Clock skew and jitter

Skew. Two clues: (1) it is a difference between two different nodes (spatial), and (2) it is the same every cycle (deterministic). Jitter would be one node wobbling by a random amount each cycle. The word "always ... exactly" kills jitter. (The magnitude 0.080 ns is irrelevant to the classification.)

$t_{skew}>0$ (positive skew by our convention: capture clock late). Because the capturing edge is pushed to $T+t_{skew}$, the data has more time to settle → positive skew helps setup. (Remember it hurts hold — that's a later level.)

The period $==T==$ is absent. Consequence: you cannot fix a hold violation by slowing the clock — the same edge races itself, so making cycles longer changes nothing. You must add delay to the data path or cut skew.

$T_{min}=t_{cq}+t_{logic,max}+t_{su}=0.25+1.75+0.15=2.15$ ns. $f_{max}=1/2.15\text{ ns}=1/(2.15\times 10^{-9}\text{ s})\approx 465.1$ MHz. Why this order: launch reacts ($t_{cq}$), signal crosses logic ($t_{logic,max}$), and must be steady $t_{su}$ before the next tick — those three stacked end-to-end are one period.

$T_{min}=t_{cq}+t_{logic,max}+t_{su}+t_{jitter}-t_{skew}=0.25+1.75+0.15+0.06-0.10=2.11$ ns. $f_{max}=1/2.11\text{ ns}\approx 473.9$ MHz. Why signs: jitter shrinks the available window → add it (period must grow). Positive skew lends time to setup → subtract it (period can shrink). Net here: skew wins slightly, so we actually run faster than Q2.1.

LHS $=t_{cq}+t_{logic,min}=0.20+0.30=0.50$. RHS $=t_{skew}+t_h+t_{jitter}=0.05+0.35+0.04=0.44$. $0.50\ge 0.44$ ✓ → hold satisfied, margin $=0.50-0.44=0.06$ ns. Why compare these: we race the fastest new data ($t_{logic,min}$) against the skewed, jittered edge plus the hold window. If the fast data would arrive before that window closes, it corrupts the capture.

$T_{min}=t_{cq}+t_{logic,max}+t_{su}+t_{jitter}-t_{skew}=0.25+1.75+0.15+0.06-(-0.12)=0.25+1.75+0.15+0.06+0.12=2.33$ ns. $f_{max}=1/2.33\text{ ns}\approx 429.2$ MHz. Compared with Q2.2's $2.11$ ns, negative skew lengthens $T_{min}$ by $0.22$ ns. Why: a negative skew means the capture edge arrives early, so the data has less time to settle before it — the $-t_{skew}$ term becomes $+0.12$ and hurts setup. Mirror image of positive skew: early capture starves setup, late capture feeds it.

Hold requires $t_{cq}+t_{logic,min}\ge t_{skew}+t_h+t_{jitter}$. Solve for skew: $t_{skew}\le t_{cq}+t_{logic,min}-t_h-t_{jitter}=0.20+0.30-0.35-0.04=0.11$ ns. Largest safe skew $=0.11$ ns. Beyond that the late capture edge lets fast data overrun the hold window. Why isolate skew: we treat the constraint as an inequality in one unknown; everything else is fixed data, so we just move terms across.

Setup margin $=(T+t_{skew})-(t_{cq}+t_{logic,max}+t_{su}+t_{jitter})$ $=(3.0+0.11)-(0.20+2.4+0.15+0.04)=3.11-2.79=0.32$ ns. Hold margin $=(t_{cq}+t_{logic,min})-(t_{skew}+t_h+t_{jitter})=0.50-0.50=0.00$ ns. Hold margin is $0$ — hold is the binding constraint (right at the edge). Setup has a comfy 0.32 ns. Interpretation: cranking skew up bought setup room while starving hold to exactly zero. Any more skew and the chip fails hold even though setup looks great — the classic "useful skew" danger.

Lowering $f$ does nothing — hold has no $T$; the same-edge race is period-independent. The chip still fails by 0.08 ns. Correct fix: raise $t_{logic,min}$ (slow the fast path) by at least the shortfall. Add buffers giving $\ge 0.08$ ns of extra minimum delay, then LHS rises by 0.08 and margin becomes $\ge 0$. Why buffers not clock: hold demands data arrive late enough; padding the data path is the only lever that touches the LHS of the hold inequality.

(a) $T_{min}=t_{cq}+t_{logic,max}+t_{su}+t_{jitter}-t_{skew}=0.30+2.10+0.20+0.05-0.08=2.57$ ns. (b) Hold: LHS $=0.30+0.40=0.70$; RHS $=0.08+0.30+0.05=0.43$; $0.70\ge 0.43$ ✓ (margin 0.27 ns). Notice $T$ never appeared — hold is fine for any period. (c) Legal range: $T\ge 2.57$ ns (equivalently $f\le 389.1$ MHz). There is no upper bound on $T$ because hold doesn't limit it — you may run as slow as you like.

Setup needs $t_{cq}+t_{logic,max}+t_{su}+t_{jitter}\le T+t_{skew}$ $\Rightarrow t_{skew}\ge (0.30+2.05+0.18+0.05)-2.2222=2.58-2.2222=0.3578$ ns. Hold needs $t_{skew}\le t_{cq}+t_{logic,min}-t_h-t_{jitter}=0.30+0.25-0.30-0.05=0.20$ ns. Combined requirement: $0.3578\le t_{skew}\le 0.20$ — empty! No skew value satisfies both. Synthesis conclusion: at 450 MHz this path is infeasible by skew alone. You must also cut $t_{logic,max}$ (faster setup path) or add data delay to relax hold, then re-solve. Skew is a transfer, not a creator, of margin.

(a) $T_{min}=t_{cq}+t_{logic,max}+t_{su}+t_{jitter,su}-t_{skew}=0.28+1.90+0.17+0.06-0.09=2.32$ ns. $f_{max}=1/2.32\text{ ns}\approx 431.0$ MHz. (b) Hold margin $=(t_{cq}+t_{logic,min})-(t_{skew}+t_h+t_{jitter,h})=(0.28+0.35)-(0.09+0.28+0.03)=0.63-0.40=0.23$ ns ✓. (c) Halving jitter: $t_{jitter,su}=0.03$. New $T_{min}=0.28+1.90+0.17+0.03-0.09=2.29$ ns → $f_{max}=1/2.29\text{ ns}\approx 436.7$ MHz. Cleaner clock (better Phase Locked Loop (PLL)) buys ~5.7 MHz here.

Define slacks: $S_{setup}=(T+t_{skew})-(t_{cq}+t_{logic,max}+t_{su}+t_{jitter})$ $S_{hold}=(t_{cq}+t_{logic,min})-(t_{skew}+t_h+t_{jitter}).$ Replace $t_{skew}\to t_{skew}+\Delta$: $S_{setup}\to S_{setup}+\Delta$ (skew appears with $+$ sign) and $S_{hold}\to S_{hold}-\Delta$ (skew appears with $-$ sign). So $\partial S_{setup}/\partial t_{skew}=+1$ and $\partial S_{hold}/\partial t_{skew}=-1$: what setup gains, hold loses, exactly. Ceiling: hold slack must stay $\ge 0$, so $\Delta$ can only grow until $S_{hold}=0$. Past that point extra skew creates a hold violation — the hard cap on "useful skew." This is exactly the boundary Static Timing Analysis tools enforce.

Show the slack: using the setup-slack formula from Q5.2 with the Q5.1 numbers, $S_{setup}=(T+t_{skew})-(t_{cq}+t_{logic,max}+t_{su}+t_{jitter,su})$ $=(2.32+0.09)-(0.28+1.90+0.17+0.06)=2.41-2.41=0.00\text{ ns}.$ The slack is exactly $0$ because we deliberately set $T=T_{min}$ in Q5.1(a) — running at the minimum period always drives setup slack to zero. Tolerable increase: any rise $\delta$ in $t_{logic,max}$ makes $S_{setup}=-\delta <0$. So the tolerable increase is $0.00$ ns — even a hair slower and metastability risk begins. Lesson: running at exactly $T_{min}$ leaves zero setup guard-band; real designs keep a positive margin precisely so a slightly slow path can't trigger Metastability.

You raced two clock edges against a chain of delays. Setup = data mustn't be too slow (fear the max path; add jitter, subtract positive skew, add negative skew). Hold = data mustn't be too fast (fear the min path; skew and jitter both hurt; no $T$ anywhere). Skew is a see-saw: tilt toward setup and hold sags, exactly one-for-one. Jitter is pure loss on both sides. Metastability is what you get when you tilt too far and a slack goes negative.