Sequential Circuits

Question 1 (10)

(a) NOR SR latch: two cross-coupled NOR gates; $S$ into one, $R$ into the other; outputs $Q,\bar Q$. (1 for structure)

Next-state table (active-high, NOR latch): (3 for correct table)

Forbidden is $S=R=1$: it forces both outputs to 0, violating $Q=\overline{\bar Q}$; and on releasing to $0,0$ the final state is unpredictable (race), depending on gate delays. (1 for why)

(b) A gated D latch is level-sensitive/transparent: while the enable is asserted, $Q$ follows $D$ continuously. An edge-triggered D flip-flop samples $D$ only at the active clock edge (the sampling instant) and holds it otherwise — it is never transparent. (3: transparency 1, sampling instant 1, correct contrast 1)

(c) JK: on hold $Q^{+}=Q$, set when $J=1$, reset when $K=1$, toggle when $J=K=1$. $Q^{+}=J\bar Q + \bar K Q.$ (2)

Question 2 (12)

(a) Setup constraint: $T \ge t_{cq}+t_{pd}+t_{su}$. (1) $T_{min}=90+520+60=670\text{ ps}.$ (2) $f_{max}=1/670\text{ps}\approx 1.493\text{ GHz}.$ (1)

(b) Hold constraint: $t_{cq}+t_{cd}\ge t_{h}$. (1) $90+45=135\text{ ps}\ge 40\text{ ps} \Rightarrow \text{satisfied (margin }95\text{ ps).}$ (2) If it had failed, fix = add buffer/delay on data path (increase $t_{cd}$). (1)

(c) Positive skew (receiver clock later by $t_{skew}$): Setup: $T \ge t_{cq}+t_{pd}+t_{su}-t_{skew}$ → skew relaxes setup. (1) $T_{min}=670-35=635\text{ ps}.$ (1) Hold: $t_{cq}+t_{cd}\ge t_{h}+t_{skew}$ → skew tightens hold. New required: $t_h+t_{skew}=75$ ps; available $135$ ps → margin $=135-75=60$ ps, still satisfied. (2)

Question 3 (12)

(a) Mod-6 counts $000\to001\to010\to011\to100\to101\to000$. T flip-flop toggles when $T=1$; $T_i=Q_i\oplus Q_i^{+}$. (2 for table)

Derive (states 110,111 are don't-cares): (4 for correct simplified equations)

• $T_0=1$ (toggles every cycle). ✔ all listed states have $T_0=1$.
• $T_1$: =1 for rows 001,011,101 → whenever $Q_0=1$ except when returning… check: 001→$T_1=1$, 011→$T_1=1$, 101→$T_1=0$. So $T_1 = Q_0\bar Q_2$ (with don't-cares).
• $T_2$: =1 for 011 and 101 → $T_2 = Q_1Q_0 + Q_2Q_0 = Q_0(Q_1+Q_2)$.

Final: $\;T_0=1,\quad T_1=Q_0\bar Q_2,\quad T_2=Q_0(Q_1+Q_2).$ (2 for using don't-cares/simplification)

(b) In a synchronous counter all flip-flops share the clock, so worst-case is one $t_{cq}$ plus next-state logic — outputs settle together. In a ripple counter each stage clocks the next, so delays add: bit 0's transition ripples through. Worst-case output-valid delay $\approx n\cdot t_{cq}$ (here up to $3\,t_{cq}$ for 3 stages), and glitches/transient wrong codes appear. (4: mechanism 2, ripple delay expression 2)

Question 4 (8)

(a) 4-bit Johnson feeds inverted MSB into LSB. Sequence from 0000: (3) $0000\to1000\to1100\to1110\to1111\to0111\to0011\to0001\to0000.$ Modulus $=2\times4=8$. (1)

(b) Ring (one-hot circulating 1): 4 distinct states, single-bit decode (1 gate/no gate). Johnson: 8 states, each decoded with a 2-input gate (adjacent-bit pattern). (2)

(c) Both have unused states forming isolated loops the counter can lock into on power-up/glitch; ring counter has $2^4-4=12$ unused states, Johnson $2^4-8=8$. Self-correction: add logic to force a legal state (e.g., steer into the sequence when an illegal pattern is detected). (2)

Question 5 (12)

(a) Mealy 101 detector, states: S0 (nothing), S1 (saw 1), S2 (saw 10). Output on transition. (4 table + 2 diagram)

(Overlap handled: from S2 on 1 we output 1 and go to S1, since that 1 can start a new 101.) (6)

(b) Mealy output depends on state and current input, so the 1 appears combinationally in the same cycle the last bit arrives (faster, fewer states — 3 here). Moore output depends on state only, needs an extra "detected" state, giving output one cycle later and typically more states (4). (3)

(c) Minimisation: A,B,C,D. Group by output: {A,B,C} out=0, {D} out=1.

• Check within {A,B,C}: A→(B,C), C→(B,C) identical ⇒ A≡C. B→(B,D): D is in different group ⇒ B not equivalent to A/C. Reduced states: {A,C}=P, {B}=Q, {D}=R. (2)

4 states → 3 states. (1)

Question 6 (6)

(a) Metastability: a flip-flop clocked while its data violates setup/hold can enter a balanced state between 0 and 1, resolving after an unbounded time. A 2-FF synchroniser gives the first FF a full clock period to resolve before the second samples it, exponentially lowering failure probability — but since resolution time is only probabilistic (exponential tail), it can never be zero. (3)

(b) $MTBF=\dfrac{e^{t_r/\tau}}{f_c f_d T_0}$ with $t_r/\tau=2.0/0.10=20$. $e^{20}\approx 4.852\times10^{8};\quad f_c f_d T_0=10^{8}\cdot10^{7}\cdot10^{-9}=10^{6}.$ $MTBF\approx 4.852\times10^{8}/10^{6}=4.85\times10^{2}\text{ s}\approx 485\text{ s}.$ (2) Extra stage adds $t_r=1.0$ ns → factor $e^{1.0/0.10}=e^{10}\approx 2.20\times10^{4}$ improvement. Yes, hugely improves. (1)

[
 {"claim":"Setup Tmin=670ps, fmax≈1.4925GHz","code":"tcq=90;tpd=520;tsu=60;Tmin=tcq+tpd+tsu;fmax=1/(Tmin*1e-12);result=(Tmin==670 and abs(fmax-1.4925e9)<1e7)"},
 {"claim":"Hold satisfied margin 95ps and skew hold margin 60ps","code":"tcq=90;tcd=45;th=40;skew=35;m1=tcq+tcd-th;m2=tcq+tcd-(th+skew);result=(m1==95 and m2==60)"},
 {"claim":"Skew setup Tmin=635ps","code":"result=(670-35==635)"},
 {"claim":"Johnson 4-bit modulus is 8","code":"result=(2*4==8)"},
 {"claim":"MTBF approx 485s","code":"import sympy as sp;tr=sp.Rational(20,10);tau=sp.Rational(1,10);num=sp.exp(tr/tau);den=sp.Integer(10)**6;mtbf=float(num/den);result=(abs(mtbf-485)<5)"},
 {"claim":"Extra stage improvement factor e^10≈2.20e4","code":"import sympy as sp;f=float(sp.exp(10));result=(abs(f-2.2026e4)<50)"}
]