A flip-flop is not magic. When the clock edge arrives, the output Q Q Q not change instantly. Electrons take time to flow through the internal transistors. The clock-to-Q delay (t c q t_{cq} t c q Q Q Q
WHY it exists: transistors have capacitance; charging/discharging a node takes real physical time.
WHY we care: every clock period must be long enough for this delay plus the logic plus the setup margin, or the circuit breaks.
Definition Clock-to-Q delayt c q t_{cq} t c q active clock edge to the moment the flip-flop's output Q Q Q valid and stable at its new value.
Measured from the clock edge (usually the rising edge, at the 50% voltage point).
Measured to Q Q Q
There are actually two numbers manufacturers give:
Imagine two flip-flops with a block of combinational logic between them, all sharing one clock.
HOW the signal travels each cycle:
Clock edge hits FF1 → after t p c q t_{pcq} t p c q Q 1 Q_1 Q 1
Q 1 Q_1 Q 1 t p d t_{pd} t p d FF2 needs its input stable before its own clock edge, by the setup time t s e t u p t_{setup} t se t u p
For the data to arrive in time for the next edge (one period T c T_c T c
t p c q ⏟ FF1 launches + t p d ⏟ logic + t s e t u p ⏟ FF2 catches ≤ T c \underbrace{t_{pcq}}_{\text{FF1 launches}} + \underbrace{t_{pd}}_{\text{logic}} + \underbrace{t_{setup}}_{\text{FF2 catches}} \;\le\; T_c FF1 launches t p c q + logic t p d + FF2 catches t se t u p ≤ T c
And the hold side (using the fast delay t c c q t_{ccq} t cc q
Worked example Example 1 — Find max frequencyGiven: t p c q = 30 t_{pcq} = 30 t p c q = 30 t s e t u p = 20 t_{setup} = 20 t se t u p = 20 t p d = 100 t_{pd} = 100 t p d = 100 T c ≥ 30 + 100 + 20 = 150 ps T_c \ge 30 + 100 + 20 = 150\ \text{ps} T c ≥ 30 + 100 + 20 = 150 ps Why add all three? Each is a mandatory delay in one cycle.
f m a x = 1 150 ps = 1 150 × 10 − 12 ≈ 6.67 GHz f_{max} = \frac{1}{150\ \text{ps}} = \frac{1}{150\times10^{-12}} \approx 6.67\ \text{GHz} f ma x = 150 ps 1 = 150 × 1 0 − 12 1 ≈ 6.67 GHz Why invert? Frequency is cycles per second = 1 / period 1/\text{period} 1/ period
Worked example Example 2 — Does hold hold?Given: t c c q = 10 t_{ccq} = 10 t cc q = 10 t h o l d = 25 t_{hold} = 25 t h o l d = 25 t p d , min = 5 t_{pd,\min} = 5 t p d , m i n = 5 t c c q + t p d , min = 10 + 5 = 15 t_{ccq} + t_{pd,\min} = 10 + 5 = 15 t cc q + t p d , m i n = 10 + 5 = 15 ≥ t h o l d = 25 \ge t_{hold} = 25 ≥ t h o l d = 25 15 < 25 15 < 25 15 < 25 HOLD VIOLATION ❌
Why this step? Data reaches FF2 after only 15 ps, but FF2 needs it held for 25 ps — the new value clobbers the old one before FF2 grabs it. Fix: add buffer delay to the short path.
Worked example Example 3 — Budget the logicA chip must run at 2 2 2 t p c q = 40 t_{pcq}=40 t p c q = 40 t s e t u p = 30 t_{setup}=30 t se t u p = 30 T c = 1 2 × 10 9 = 500 ps T_c = \frac{1}{2\times10^9} = 500\ \text{ps} T c = 2 × 1 0 9 1 = 500 ps t p d , max ≤ T c − t p c q − t s e t u p = 500 − 40 − 30 = 430 ps t_{pd,\max} \le T_c - t_{pcq} - t_{setup} = 500 - 40 - 30 = 430\ \text{ps} t p d , m a x ≤ T c − t p c q − t se t u p = 500 − 40 − 30 = 430 ps Why subtract? The flip-flops "eat" 70 ps of the budget; the rest is free for logic.
Common mistake "Q changes instantly on the clock edge."Why it feels right: In an idealized textbook truth table, Q Q Q The fix: Real gates have delay. Q Q Q t c q t_{cq} t c q after the edge. Ignoring it overestimates f m a x f_{max} f ma x
Common mistake "Use the samet c q t_{cq} t c q Why it feels right: It's one flip-flop, so one delay, right?
The fix: Setup (slowest path) uses max t p c q t_{pcq} t p c q min t c c q t_{ccq} t cc q
Common mistake "Adding delay always hurts."Why it feels right: Delay slows things down.
The fix: For hold violations, adding delay to the short path is the standard fix — it doesn't affect f m a x f_{max} f ma x long path).
Recall Feynman: explain to a 12-year-oldImagine a relay race. When the starting whistle blows (the clock edge), the runner (flip-flop) doesn't teleport — it takes a moment to react and start running. That reaction moment is the clock-to-Q delay. The whole lap (one clock tick) has to be long enough for this reaction, plus the running (logic), plus the next runner getting ready to grab the baton (setup). If the lap is too short, someone drops the baton — the circuit gives wrong answers.
"Q Comes Quick, but not Quicker than t c q t_{cq} t c q
For the timing budget: PLS ≤ Tc → P cq + L ogic + S etup ≤ Clock period.
What is clock-to-Q delay t c q t_{cq} t c q Time from the active clock edge until output
Q Q Q is valid and stable.
Which delay does the setup / max-frequency check use, min or max? Maximum (
t p c q t_{pcq} t p c q ), the propagation clock-to-Q delay (worst case).
Which delay does the hold check use? Minimum (
t c c q t_{ccq} t cc q ), the contamination clock-to-Q delay (earliest Q changes).
Write the minimum clock period inequality. T c ≥ t p c q + t p d + t s e t u p T_c \ge t_{pcq} + t_{pd} + t_{setup} T c ≥ t p c q + t p d + t se t u p .
Write the hold-time constraint. t c c q + t p d , min ≥ t h o l d t_{ccq} + t_{pd,\min} \ge t_{hold} t cc q + t p d , m i n ≥ t h o l d .
Why doesn't Q change instantly on the clock edge? Internal transistor capacitances must charge/discharge, which takes physical time.
How do you fix a hold violation? Add delay (buffers) to the short combinational path so data arrives late enough.
t p c q = 30 t_{pcq}=30 t p c q = 30 t p d = 100 t_{pd}=100 t p d = 100 t s e t u p = 20 t_{setup}=20 t se t u p = 20 f m a x f_{max} f ma x 1 / 150 ps ≈ 6.67 1/150\text{ps} \approx 6.67 1/150 ps ≈ 6.67 GHz.
Relation between t c c q t_{ccq} t cc q t p c q t_{pcq} t p c q t c c q ≤ t p c q t_{ccq} \le t_{pcq} t cc q ≤ t p c q (contamination ≤ propagation).
Setup and Hold Time — the other two timing parameters; t c q t_{cq} t c q Flip-Flops — the device whose output delay this describes.Combinational Logic Delay — the t p d t_{pd} t p d Maximum Clock Frequency — directly derived using t c q t_{cq} t c q Timing Analysis — the overall framework of setup/hold/clock-to-Q.Clock Skew — modifies these equations when clock arrives at different times.
Tc >= tpcq + tpd + tsetup
Intuition Hinglish mein samjhoDekho, flip-flop ek chhota memory element hai. Jab clock ka edge aata hai (rising edge), toh output Q Q Q clock-to-Q delay (t c q t_{cq} t c q
Yeh important kyun hai? Kyunki ek clock period (T c T_c T c t p c q t_{pcq} t p c q t p d t_{pd} t p d t s e t u p t_{setup} t se t u p T c ≥ t p c q + t p d + t s e t u p T_c \ge t_{pcq} + t_{pd} + t_{setup} T c ≥ t p c q + t p d + t se t u p
Ek twist yaad rakhna: setup/max-frequency check ke liye max delay (t p c q t_{pcq} t p c q hold check ke liye min delay (t c c q t_{ccq} t cc q t c c q + t p d , min ≥ t h o l d t_{ccq} + t_{pd,\min} \ge t_{hold} t cc q + t p d , m i n ≥ t h o l d
Bas yaad rakho: Q instant nahi badalta, real delay hota hai, aur yeh delay har timing calculation ka pehla term hai. Yahi 20% concept 80% timing problems solve kar dega.
