Visual walkthrough — Clock-to-Q delay

Step 1 — What a clock edge actually looks like

WHAT. A clock is just a voltage that marches up and down forever: low, high, low, high. The moment it jumps from low to high is called the rising edge. That upward jump is not vertical in real life — the voltage climbs a ramp. We agree to say "the edge happened" at the exact instant the voltage crosses halfway up (the 50% point).

WHY. Every timing number in this note is measured from this halfway crossing. If we started counting from "somewhere on the ramp," different engineers would get different answers. The 50% point is a fair, agreed-upon starting gun.

PICTURE. In the figure below, the clock ramps up; the pink dot marks the 50% crossing. That dot is time-zero for everything that follows.

Step 2 — The output Q reacts late: this delay is $t_{cq}$

WHAT. A flip-flop is a memory cell. On the rising edge it copies its input onto its output $Q$. But $Q$ does not snap over at the same instant — it waits a little, then ramps to its new level. The gap from the clock's 50% point to $Q$'s 50% point is the clock-to-Q delay, written $t_{cq}$.

WHY this gap exists. Inside the flip-flop are tiny switches (transistors). Each has capacitance — think of it as a tiny bucket that must fill with charge before the wire's voltage moves. Filling a bucket takes real time. So $Q$ physically cannot move instantly.

WHY we measure edge-50% to Q-50%. Same fairness reason as Step 1 — halfway to halfway is a clean, repeatable ruler.

PICTURE. Two waveforms stacked: the clock on top with its 50% dot, $Q$ below with its own 50% dot. The horizontal arrow between the two dots is $t_{cq}$.

$Q\text{ valid at time }=\underset{\text{clock edge (50\%)}}{\underbrace{0}}+\underset{\text{the react time}}{\underbrace{t_{cq}}}$

Here $0$ is our start-of-timing instant, and $t_{cq}$ is the delay we just drew as the arrow.

Step 3 — There are really TWO delays: fastest and slowest

WHAT. No two flip-flops react in exactly the same time — temperature, voltage, and manufacturing wobble spread it out. So a datasheet gives a band:

• $t_{ccq}$ = the earliest $Q$ can even begin to move (contamination — "when does Q first get dirty?").
• $t_{pcq}$ = the latest $Q$ is fully valid (propagation — worst case).

They always obey $t_{ccq}\le t_{pcq}$.

WHY two. Different questions need different ends of the band. "Will the signal arrive in time?" is a worst-case (slowest) question → use $t_{pcq}$. "Might the signal arrive too early and wreck stored data?" is a best-case (fastest) question → use $t_{ccq}$. Using one number for both would hide half the danger.

PICTURE. One clock edge, and a shaded band on $Q$: its left wall is $t_{ccq}$ (Q starts changing), its right wall is $t_{pcq}$ (Q settled). $Q$ is only guaranteed valid to the right of the right wall.

$\underset{\text{Q starts moving (min)}}{\underbrace{t_{ccq}}}\le \underset{\text{Q fully valid (max)}}{\underbrace{t_{pcq}}}$

Step 4 — Build the racetrack: two flip-flops with logic between

WHAT. Real circuits chain flip-flops. Draw FF1, then a cloud of combinational logic, then FF2. All three share the same clock wire. Each clock tick, data must run from FF1's output, through the logic, into FF2's input.

WHY this exact shape. This "launch flop → logic → capture flop" is the atom of every synchronous chip. If we get the timing right for one such hop, we've got it right everywhere.

PICTURE. FF1 (launch) on the left, the logic cloud in the middle labelled with its delay, FF2 (capture) on the right. The single clock feeds both flops from below — remember that, it matters in Step 5.

Step 5 — The setup race: data must arrive before the next edge

WHAT. FF2 also needs its input to be steady for a moment before its own clock edge — that quiet window is the setup time, $t_{setup}$ (see Setup and Hold Time). Now walk the signal along the timeline of one clock period $T_c$ (the time between one rising edge and the next):

1. Edge fires. After $t_{pcq}$, FF1's output $Q_1$ is valid. → arrives at time $t_{pcq}$.
2. $Q_1$ crosses the logic cloud, taking $t_{pd}$. → arrives at FF2's input at $t_{pcq}+t_{pd}$.
3. This must land at least $t_{setup}$ before the next edge, which is at time $T_c$.

WHY worst case. For "does it make it in time?", assume the slowest launch and the slowest logic — if even the slowpokes arrive on time, everyone does. So we use $t_{pcq}$ and $t_{pd,\max }$.

PICTURE. A single timeline from one edge (left) to the next edge (right, at $T_c$). Coloured bars stack left-to-right: lavender $t_{pcq}$, coral $t_{pd}$, mint $t_{setup}$. The mint bar's right wall must not pass the next edge. The gap left over is slack.

Reading the bars off the picture directly:

$\underset{\text{FF1 launches}}{\underbrace{t_{pcq}}}+\underset{\text{logic crosses}}{\underbrace{t_{pd,\max }}}+\underset{\text{FF2’s quiet window}}{\underbrace{t_{setup}}}\le \underset{\text{one clock period}}{\underbrace{T_c}}$

Rearrange (subtract nothing — just read it as a lower bound on $T_c$):

Step 6 — The hold race: data must NOT arrive too soon

WHAT. There is an opposite danger. When the edge fires, FF2 is also trying to grab its old input value. If new data from FF1 races through fast logic and reaches FF2 too quickly, it overwrites the old value before FF2 has captured it — that quiet-window after the edge is the hold time, $t_{hold}$.

WHY fastest case. This is a "too early" problem, so we assume the fastest everything: earliest launch $t_{ccq}$ and shortest logic $t_{pd,\min }$. If even the fastest path is not too fast, we're safe.

PICTURE. Same edge at time-zero. A tiny window of width $t_{hold}$ sits just after the edge (the "keep old data still" zone). The new data's earliest arrival is at $t_{ccq}+t_{pd,\min }$ — its wall must land outside (to the right of) the hold window.

Step 7 — Degenerate & edge cases (every scenario covered)

WHAT & WHY (each case with its own reasoning):

Worked example woven through the pictures

The one-picture summary

Everything on one timeline: the lavender/coral/mint bars for the setup race stretching toward the next edge, and the small hold window right after the edge for the hold race — one drawing that holds the entire derivation.

Active recall

Connections

• Setup and Hold Time — the two quiet windows the races run against.
• Flip-Flops — the launching/capturing device.
• Combinational Logic Delay — the $t_{pd}$ bars.
• Maximum Clock Frequency — the inverse of the setup sum.
• Timing Analysis — the framework tying all races together.
• Clock Skew — Case D, the $\pm t_{skew}$ correction.