Exercises — Clock-to-Q delay

WHAT: $t_{ccq}=12$ ps is the contamination clock-to-Q delay; $t_{pcq}=45$ ps is the propagation clock-to-Q delay. WHY $t_{ccq}$ smaller: contamination is the earliest moment $Q$ can start moving (the fastest internal path finishing). Propagation is the latest moment $Q$ is fully valid (the slowest path finishing). The fastest thing can never finish after the slowest thing, so $t_{ccq}\le t_{pcq}\Rightarrow 12\le 45✓$ On the figure: $t_{ccq}$ is the short blue segment on the bottom (hold) timeline; $t_{pcq}$ is the longer blue segment on the top (setup) timeline.

• Setup / max-frequency → use $t_{pcq}$ (the max, worst case). We are asking "did data finish arriving in time?" — worst case is late. This is the top timeline in the figure.
• Hold → use $t_{ccq}$ (the min, earliest). We are asking "did data arrive dangerously early?" — worst case is early. This is the bottom timeline in the figure. Mnemonic: Setup = Slow, Hold = Hasty.

False. The edge crossing 50% is where we start the stopwatch (the yellow line at the left of both timelines in the figure). $Q$ reaches its new valid value $t_{cq}$ later, because internal transistor capacitances need physical time to charge/discharge. This is the whole reason $t_{cq}>0$.

WHAT: add the three mandatory delays in one cycle — the three coloured segments of the top timeline in the figure (blue + green + red). $T_{c,\min }=t_{pcq}+t_{pd,\max }+t_{setup}=35+90+25=150\text{ps}$ WHY invert for frequency: frequency is cycles per second $=1/\text{period}$. $f_{max}=\frac{1}{150\times 10^{-12}\text{s}}\approx 6.67\times 10^9\text{Hz}=6.67\text{GHz}$

WHAT: check $t_{ccq}+t_{pd,\min }\ge t_{hold}$ — this is the bottom timeline in the figure: does the green "new data arrives" line land after the red quiet window ends? $15+20=35\ge 30✓$ WHY it passes: the earliest the new data can reach FF2 is $35$ ps after the edge, but FF2 only needs the old data held for $30$ ps. There is a $5$ ps margin — the new value does not clobber the old capture. Hold PASSES.

WHAT: find the period, then subtract the flip-flop overhead. $T_c=\frac{1}{2.5\times 10^9}=400\text{ps}$ WHY subtract: the flip-flops "eat" $t_{pcq}+t_{setup}=80$ ps of the budget; whatever remains is free for logic — on the top timeline, the green segment gets whatever the blue and red segments leave behind. $t_{pd,\max }\le 400-45-35=320\text{ps}$

WHAT: test the setup inequality. $t_{pcq}+t_{pd,\max }+t_{setup}=40+210+20=270\text{ps}$ Required: $\le T_c=250$ ps. But $270>250$ → SETUP VIOLATION ❌. WHY setup, not hold: the slow path fails to arrive before the next edge. On the top timeline, the three coloured segments overrun the yellow "next edge" line by $270-250=20$ ps. Hold failures come from fast paths arriving too early — that is a different story entirely (the bottom timeline). Fix menu: (a) slow the clock so $T_c\ge 270$ ps, or (b) shorten the logic ($t_{pd,\max }$), or (c) use a faster flip-flop (lower $t_{pcq}$).

Max frequency (uses $t_{pcq}+t_{pd,\max }+t_{setup}$): $\text{FF-A: }25+100+15=140\text{ps}\Rightarrow f=1/140\text{ps}\approx 7.14\text{GHz}$ $\text{FF-B: }20+100+12=132\text{ps}\Rightarrow f=1/132\text{ps}\approx 7.58\text{GHz}$ FF-B is faster (smaller sum ⇒ higher frequency).

Hold check (uses $t_{ccq}+t_{pd,\min }\ge t_{hold}$): $\text{FF-A: }8+10=18\ge 18✓(\text{just barely})$ $\text{FF-B: }4+10=14\ge 25?\text{No, }14<25\Rightarrow \text{VIOLATION}❌$ FF-B is more likely to cause a hold violation — it has a smaller $t_{ccq}$ (data starts moving sooner) AND a larger $t_{hold}$ (needs data held longer). Both push it toward failure. Lesson: the "faster" flip-flop for frequency can be the dangerous one for hold. You cannot judge on one number alone.

WHAT: we need $t_{ccq}+t_{pd,\min }+(\text{buffer delay})\ge t_{hold}$. Current slack deficit: $t_{hold}-(t_{ccq}+t_{pd,\min })=40-(6+12)=40-18=22\text{ps short.}$ WHY buffers: each adds $8$ ps to the short path only (leaving $f_{max}$ untouched, since that depends on the long path). We need to cover $\ge 22$ ps: $n\times 8\ge 22\Rightarrow n\ge 2.75\Rightarrow n=3\text{buffers.}$ Check: $6+12+3\times 8=6+12+24=42\ge 40✓$. Two buffers give only $34<40$ — not enough. Answer: 3 buffers.

Step 1 — the period: $T_c=\frac{1}{2\times 10^9}=500\text{ps.}$ Step 2 — setup gives the upper limit on the SLOW path: $t_{pd,\max }\le T_c-t_{pcq}-t_{setup}=500-50-40=410\text{ps.}$ Step 3 — hold gives the lower limit on the FAST path: $t_{pd,\min }\ge t_{hold}-t_{ccq}=60-20=40\text{ps.}$ Answer: every path must satisfy $40\text{ps}\le t_{pd}\le 410\text{ps.}$ WHY the two ends come from different constraints: the upper bound protects against arriving too late (setup, top timeline), the lower bound protects against arriving too early (hold, bottom timeline). A legal design keeps all logic delays inside this window.

(a) Setup with zero logic: $T_{c,\min }=t_{pcq}+0+t_{setup}=30+20=50\text{ps}\Rightarrow f_{max}=\frac{1}{50\text{ps}}=20\text{GHz.}$ Even with no logic the clock cannot be infinitely fast — the flip-flops' own $t_{pcq}+t_{setup}$ sets a hard ceiling. This is the register-to-register floor of any technology. (b) Hold with zero logic: $t_{ccq}+t_{pd,\min }=10+0=10\ge t_{hold}=35?10<35\Rightarrow \text{VIOLATION}❌$ WHY this is the worst possible hold case: with no logic to slow it, the new data races through instantly. Direct FF-to-FF connections are the classic hold-failure hotspot — you almost always need padding buffers. Deficit $=35-10=25$ ps must be added.

(a) POSITIVE skew, $t_{skew}=+15$ ps (FF2 edge late — helps setup, hurts hold): Setup: $T_{c,\min }=t_{pcq}+t_{pd,\max }+t_{setup}-t_{skew}=30+100+20-15=135\text{ps}\Rightarrow f_{max}=1/135\text{ps}\approx 7.41\text{GHz.}$ Hold: $t_{ccq}+t_{pd,\min }=10+8=18\ge t_{hold}+t_{skew}=25+15=40?18<40\Rightarrow \text{VIOLATION}❌$

(b) NEGATIVE skew, $t_{skew}=-15$ ps (FF2 edge early — hurts setup, helps hold): Setup: $T_{c,\min }=t_{pcq}+t_{pd,\max }+t_{setup}-t_{skew}=30+100+20-(-15)=165\text{ps}\Rightarrow f_{max}=1/165\text{ps}\approx 6.06\text{GHz.}$ Hold: $t_{ccq}+t_{pd,\min }=18\ge t_{hold}+t_{skew}=25+(-15)=10?18\ge 10✓$

WHY the mirror image: the two skew signs are exact opposites. Positive skew buys frequency (smaller $T_{c,\min }$) but spends hold margin. Negative skew loses frequency (larger $T_{c,\min }$) but gains hold safety. $t_{cq}$ sits at the fulcrum of this see-saw — you cannot tilt one side without tilting the other.

WHAT: with positive skew the hold constraint tightens to $t_{ccq}+t_{pd,\min }+n\cdot 9\ge t_{hold}+t_{skew}$. $8+0+9n\ge 30+10=40\Rightarrow 9n\ge 32\Rightarrow n\ge 3.56\Rightarrow n=4.$ Check with 4 buffers: $8+4\times 9=8+36=44\ge 40✓$, margin $=44-40=4$ ps. Three buffers give $8+27=35<40$ — fails. Answer: 4 buffers, 4 ps of margin. WHY more than the no-skew case: the positive skew adds its own $10$ ps to the hold requirement, so you must pad the short path even more heavily. This is the L5 punchline: chasing frequency with positive skew silently raises the buffer bill on every short path.