Foundations — Clock-to-Q delay

Before you can read the parent note, you need to already "own" a pile of little symbols and pictures. This page builds every single one of them from zero, in the order that each one leans on the one before it. If a smart 12-year-old reads from line one, nothing should feel like a magic word.

0. The very first picture: a wire that carries a signal

Everything in digital hardware is a wire carrying a voltage. We only care about two levels:

• a high voltage → we call it 1 (or "true", or "on"),
• a low voltage → we call it 0 (or "false", or "off").

Look at the figure: the horizontal axis is time flowing to the right, and the line jumps between the low level (0) and the high level (1). That jump is never a perfect vertical cliff in real life — it's a slope — and that slope is the seed of every delay we'll meet. Remember it.

1. The clock — the drummer that sets the beat

In the figure, notice two brand-new words attached to the clock picture:

• Edge — the moment the clock changes level. A rising edge is where it goes $0\to 1$ (climbs up); a falling edge is where it goes $1\to 0$ (drops down).
• Period — the time for one full up-and-down, one whole "beat".

Why the topic needs this: the entire clock-to-Q idea is "how long after the active edge does something happen?" Without the edge as a starting line, there is nothing to measure from.

2. Prefixes and tiny numbers: what is a "picosecond"?

Delays inside a chip are absurdly small, so we use shorthand for tiny numbers.

Why the topic needs this: every answer in the parent note ends in "≈ 6.67 GHz" or "500 ps." You can't sanity-check those numbers unless you're fluent in ps ↔ GHz.

3. Frequency $f$ — how many beats per second

Why reciprocal, not something fancier? If one lap of a track takes $T_c$ seconds, then in one second you complete $1/T_c$ laps — pure counting, no physics. That is the only tool needed, so we pick the simplest one: division.

4. The flip-flop — the memory box

The figure shows the box with $D$ entering on the left and $Q$ leaving on the right, plus the little triangle on the clock input — that triangle is the universal symbol for "edge-triggered."

Why the topic needs this: clock-to-Q delay is literally the delay between "the edge told $Q$ to update" and "$Q$ actually shows the new value." No flip-flop, no $Q$, no topic.

5. The heart of the delay: transistors and capacitance

Why isn't the copy instant? Inside the flip-flop the wires behave like tiny buckets that must be filled or emptied with electric charge before the voltage on them counts as high or low.

Why the topic needs this: it answers the deepest "why?" — why does delay exist at all? Because charge can't teleport into a bucket.

6. The star of the show: clock-to-Q delay $t_{cq}$

Now we can name the delay itself. The notation $t_{\text{something}}$ always means "a time $t$, labelled by the subscript."

Read the figure like a story left to right (each mark is labelled in text on the figure, not by colour alone):

1. the clock rises — the dashed line labelled "active edge (start stopwatch)" marks the 50% point of the edge;
2. a little later $Q$ begins to move — the ramp labelled "Q" starts rising at the mark labelled "tccq (min, starts)";
3. $Q$ settles at its new level — the dot labelled "Q at 50% (stop stopwatch)", at the mark labelled "tpcq (max, valid)". The double-arrow labelled "tcq" spans the gap between the two stopwatch marks.

Why two numbers, not one? Some later checks need the worst-case-slow delay (will it finish in time?), others need the worst-case-fast delay (did it change too soon?). One number can't play both roles — see the mermaid map below.

7. The companions: $t_{pd}$, $t_{cd}$, $t_{setup}$, $t_{hold}$

These come from the neighbouring topics but the parent note uses them, so we define them here. Note the matching pair of ideas: just as the flip-flop's output has a fast flavour ($t_{ccq}$) and a slow flavour ($t_{pcq}$), so does the logic between flip-flops.

Why the topic needs these: the master timing equation is a "worst-case-slow" sum — every delay in it is a slow/propagation number, because we must make the period long enough even on the slowest day: $t_{pcq}+t_{pd}+t_{setup}\le T_c$ that is "slowest launch + slowest travel + catch margin must fit in one beat." The hold check instead mixes the fast/contamination numbers: $t_{ccq}+t_{cd}\ge t_{hold}$. You cannot read either line until all four companions are defined — which they now are.

Prerequisite map

The diagram below is drawn with Mermaid. If your reader doesn't render Mermaid, read the plain-text dependency list first — it carries the same information:

• Signal → clock edge & 50% point → clock period $T_c$ → frequency $f=1/T_c$ → max frequency $f_{max}$.
• Capacitance + flip-flop + clock edge → clock-to-Q delay $t_{cq}$, which splits into $t_{ccq}$ (min) and $t_{pcq}$ (max).
• $t_{pcq}$, logic $t_{pd}$, setup $t_{setup}$, and $f_{max}$ → the setup / max-frequency equation.
• $t_{ccq}$, logic $t_{cd}$, and hold $t_{hold}$ → the hold-time constraint.

Equipment checklist

Test yourself — cover the right side. If any answer surprises you, re-read that section before opening the parent note.

Connections

• 3.4.06 Clock-to-Q delay (Hinglish) — same foundations in Hinglish.
• Flip-Flops — the device that owns $D$, $Q$, and the clock input.
• Setup and Hold Time — where $t_{setup}$ and $t_{hold}$ come from.
• Combinational Logic Delay — the origin of $t_{pd}$ and $t_{cd}$.
• Maximum Clock Frequency — built directly from $f_{max}=1/T_{c,\min }$.
• Timing Analysis — the framework these symbols feed into.
• Clock Skew — a later twist once the edge doesn't arrive everywhere at once.