Clock-to-Q delay: Worked examples — Hardware deep dive

This is the practice arena for Clock-to-Q delay. The parent note built the two equations; here we hunt down every kind of case they can throw at you and solve each one from zero. Nothing new is assumed — if a symbol appears, we re-earn it.

Quick symbol refresher (each defined in the parent, repeated so you never scroll):

Definition The five delays in one place

$t_{p c q}$ = propagation clock-to-Q = slowest time from clock edge to a valid $Q$ .
$t_{cc q}$ = contamination clock-to-Q = fastest time before $Q$ even starts moving.
$t_{p d}$ = combinational logic propagation delay (with $t_{p d, m a x}$ slow path, $t_{p d, m i n}$ fast path).
$t_{se t u p}$ = how long before the edge the data must already be steady (see Setup and Hold Time).
$t_{h o l d}$ = how long after the edge the data must stay steady.
$T_{c}$ = clock period; $f = 1/ T_{c}$ is the frequency.

The scenario matrix

Think of this table as the checklist of every trap. The rest of the page fills every cell.

#	Cell class	What makes it distinct	Example
A	Setup, plain	Add three delays, invert for $f_{ma x}$	Ex 1
B	Hold, PASS	Fast path is late enough	Ex 2
C	Hold, FAIL + fix	Fast path too fast; add buffer	Ex 3
D	Logic budget	Solve backwards for allowed $t_{p d}$	Ex 4
E	Zero / degenerate	$t_{p d} = 0$ (FF straight into FF)	Ex 5
F	Limiting value	What happens as $t_{p d} \to$ its max, or $f \to \infty$ ?	Ex 6
G	Real-world word problem	CPU pipeline stage, units in GHz/ns	Ex 7
H	Exam twist: skew	Clock arrives late at FF2, both sides shift	Ex 8

We will walk A → H in order. Every numeric answer is machine-checked at the bottom.

Cell A — Setup / max-frequency, the plain case

Worked example Ex 1 (Cell A)

A path has $t_{p c q} = 35$ ps, worst-case logic $t_{p d, m a x} = 90$ ps, $t_{se t u p} = 25$ ps. Find $T_{c, m i n}$ and $f_{ma x}$ .

Forecast: guess whether $f_{ma x}$ lands above or below 10 GHz before reading on.

Add the three mandatory delays. $T_{c, m i n} = t_{p c q} + t_{p d, m a x} + t_{se t u p} = 35 + 90 + 25 = 150 ps$ Why this step? In one clock period the signal must (a) leave FF1, (b) cross the logic, (c) settle before FF2's next edge. Skip any term and you'd pretend that delay is free — the hardware disagrees.
Invert to get frequency. $f_{ma x} = \frac{1}{T _{c, m i n}} = \frac{1}{150 \times 1 0 ^{- 12} s} = 6. \overline{6} \times 1 0^{9} Hz \approx 6.67 GHz$ Why invert? Frequency = cycles per second = $1/ (seconds per cycle)$ . A longer period means a lower top speed.

Verify: units check — $1/ s = Hz$ . ✓ And $6.67 GHz \times 150 ps = 6.67 \times 1 0^{9} \times 150 \times 1 0^{- 12} = 1.0005 \approx 1$ cycle. ✓

Cell B — Hold check that PASSES

The picture below is the whole hold story in one glance. Look at the two arrows racing.

Cell C — Hold check that FAILS, then the fix

Worked example Ex 3 (Cell C — FAIL + repair)

$t_{cc q} = 10$ ps, $t_{p d, m i n} = 5$ ps, $t_{h o l d} = 30$ ps. Does hold pass? If not, how much buffer delay fixes it?

Forecast: guess the sign of the slack.

Earliest arrival. $t_{cc q} + t_{p d, m i n} = 10 + 5 = 15 ps$
Compare. $15 ps < t_{h o l d} = 30 ps \Rightarrow HOLD VIOLATION ❌$ Why a violation? New data reaches FF2 at 15 ps, but FF2 needs the old value held until 30 ps. The new value clobbers the old one 15 ps too early.
Compute the buffer needed. We must push the fast path later by the slack deficit: $t_{b u f f er} \geq t_{h o l d} - (t_{cc q} + t_{p d, m i n}) = 30 - 15 = 15 ps$ Why add to the SHORT path? Slowing the fast path delays the "poison" until after the window closes. Crucially, this does not touch $t_{p d, m a x}$ (the long path), so $f_{ma x}$ is untouched — see Maximum Clock Frequency.

Verify: after fix, $t_{cc q} + t_{p d, m i n} + t_{b u f f er} = 10 + 5 + 15 = 30 \geq 30$ . Slack $= 0$ , exactly on the edge — legal. ✓

Cell D — Solve backwards for the logic budget

Cell E — Zero / degenerate input ( $t_{p d} = 0$ )

Worked example Ex 5 (Cell E — direct FF-to-FF, no logic)

Two flip-flops wired back-to-back (a shift register): no combinational logic, so $t_{p d, m a x} = t_{p d, m i n} = 0$ . Given $t_{p c q} = 35$ ps, $t_{cc q} = 15$ ps, $t_{se t u p} = 25$ ps, $t_{h o l d} = 20$ ps. Check both sides.

Forecast: with zero logic, which check is at risk — setup or hold?

Setup side. $T_{c, m i n} = t_{p c q} + 0 + t_{se t u p} = 35 + 25 = 60 ps \Rightarrow f_{ma x} = \frac{1}{60 ps} \approx 16.67 GHz$ Why it's fine: removing logic only shortens the required period, i.e. raises $f_{ma x}$ . Setup gets easier as $t_{p d} \to 0$ .
Hold side. $t_{cc q} + t_{p d, m i n} = 15 + 0 = 15 ps \geq t_{h o l d} = 20 ps ? 15 < 20 \Rightarrow FAIL ❌$ Why it breaks: with zero logic the new data arrives at its absolute earliest ( $t_{cc q}$ ). This is the classic shift-register hold hazard — needs $t_{cc q} \geq t_{h o l d}$ , and here it isn't.
Minimum buffer: $t_{h o l d} - t_{cc q} = 20 - 15 = 5$ ps of delay on the wire.

Verify: degenerate limit sanity — as $t_{p d} \to 0$ , setup constraint $\to t_{p c q} + t_{se t u p}$ (its easiest), hold constraint $\to t_{cc q} \geq t_{h o l d}$ (its hardest). Opposite directions. ✓ Numbers: $35 + 25 = 60$ ✓; $15 < 20$ ✓; buffer $= 5$ ✓.

Cell F — Limiting behaviour

Worked example Ex 6 (Cell F — pushing

$t_{p d}$ to its ceiling) Fixed $t_{p c q} = 40$ ps, $t_{se t u p} = 20$ ps, $T_{c} = 300$ ps. As logic grows, $f_{ma x}$ falls. (a) What is the maximum legal $t_{p d, m a x}$ ? (b) What frequency results if logic is pushed 1 ps over that ceiling?

Forecast: will 1 ps over the ceiling matter noticeably?

Ceiling logic at this period. $t_{p d, m a x} = T_{c} - t_{p c q} - t_{se t u p} = 300 - 40 - 20 = 240 ps$ Why this is the limit: at exactly this $t_{p d}$ , slack is zero — any more and the data misses the edge.
Push 1 ps over → the actual period the circuit now needs. $T_{c, needed} = 40 + 241 + 20 = 301 ps \Rightarrow f = \frac{1}{301 ps} \approx 3.322 GHz$ Why it "works" but slower: the circuit isn't broken — it just can't be clocked faster than $1/301 ps$ . At the requested $300$ ps period, slack $= - 1$ ps → violation.

Verify: at the ceiling, $40 + 240 + 20 = 300 = T_{c}$ (slack $0$ ). ✓ Over the ceiling, required period $301 > 300$ , so the $300$ ps clock fails; new safe $f \approx 3.322$ GHz. ✓

Cell G — Real-world word problem

Cell H — Exam twist: clock skew

The figure shows why skew rewrites both equations: FF2's clock edge no longer lines up with FF1's.

Worked example Ex 8 (Cell H — skew both ways)

$t_{p c q} = 40$ , $t_{p d, m a x} = 120$ , $t_{se t u p} = 30$ , $t_{cc q} = 15$ , $t_{p d, m i n} = 10$ , $t_{h o l d} = 20$ (all ps), with $t_{s k e w} = 25$ ps (clock late at FF2). (a) New $T_{c, m i n}$ . (b) Does hold still pass?

Forecast: one side improves, one worsens — predict which fails, if any.

Setup with skew. $T_{c, m i n} = 40 + 120 + 30 - 25 = 165 ps$ Why subtract skew? The late FF2 edge donates $25$ ps back to the data budget, shrinking the required period. Faster clock allowed.
Hold with skew. $t_{cc q} + t_{p d, m i n} = 15 + 10 = 25 ps vs t_{h o l d} + t_{s k e w} = 20 + 25 = 45 ps$ $25 < 45 \Rightarrow HOLD VIOLATION ❌$ Why it fails now: skew pushed FF2's hold window to close at 45 ps, but the fast data still arrives at 25 ps. Skew turned a passing hold check into a failure.

Verify: without skew, hold was $25 \geq 20$ ✓ (slack $+ 5$ ); adding $t_{s k e w} = 25$ makes required $= 45$ , slack $= 25 - 45 = - 20$ ❌. Setup slack improved by exactly $25$ ps. ✓

Active recall

Recall Cover the answers

Which delays does a hold check use? ::: The minimum pair: $t_{cc q}$ and $t_{p d, m i n}$ . Ex 1: $t_{p c q} = 35, t_{p d} = 90, t_{se t u p} = 25$ ps → $f_{ma x}$ ? ::: $1/150 ps \approx 6.67$ GHz. Ex 3 buffer needed for hold? ::: $30 - (10 + 5) = 15$ ps on the short path. Ex 4 max logic at 2.5 GHz, $t_{p c q} = 45, t_{se t u p} = 30$ ? ::: $400 - 75 = 325$ ps. With $t_{p d} = 0$ (shift register), which check is the danger? ::: Hold — needs $t_{cc q} \geq t_{h o l d}$ . Ex 7 CPU: $0.08 + 0.62 + 0.05$ ns → speed? ::: $1/0.75 ns \approx 1.333$ GHz. How does late skew at FF2 change the equations? ::: Setup $- t_{s k e w}$ (easier), hold $+ t_{s k e w}$ (harder). Ex 8 hold with 25 ps skew: pass or fail? ::: Fail — $25 < 45$ .

Connections

Clock-to-Q delay — the parent this page drills.
Setup and Hold Time — the $t_{se t u p}$ and $t_{h o l d}$ terms in every example.
Combinational Logic Delay — the $t_{p d, m a x}$ / $t_{p d, m i n}$ inputs.
Maximum Clock Frequency — computed in Cells A, E, F, G.
Timing Analysis — the setup-vs-hold framing behind the scenario matrix.
Clock Skew — the Cell H twist.
Flip-Flops — the devices launching and catching the data.