Level 1 — RecognitionSequential Circuits

Sequential Circuits

⏱ 20 minutes30 marksprintable — key stays hidden on paper

Subject: Hardware | Chapter: 3.4 Sequential Circuits Difficulty: Level 1 (Recognition) Time Limit: 20 minutes Total Marks: 30

Instructions: Answer all questions. For True/False questions, a correct verdict earns 1 mark and a valid justification earns 1 mark (2 marks total). MCQs are 1 mark each unless stated.

Section A — Multiple Choice (1 mark each)

Q1. In an SR latch built from NOR gates, which input combination is the forbidden (invalid) state?

(a) S=0, R=0
(b) S=1, R=0
(c) S=0, R=1
(d) S=1, R=1

Q2. A gated D latch is transparent when:

(a) the enable signal is inactive
(b) the enable signal is active
(c) the clock has a rising edge
(d) the clock has a falling edge

Q3. The key difference between a D latch and an edge-triggered D flip-flop is:

(a) latch is level-sensitive, flip-flop is edge-sensitive
(b) latch stores 2 bits, flip-flop stores 1 bit
(c) latch has no clock
(d) flip-flop cannot store data

Q4. For a JK flip-flop, the input combination J=1, K=1 causes the output to:

(a) set to 1
(b) reset to 0
(c) hold its value
(d) toggle

Q5. A T flip-flop with T=1 behaves like:

(a) a JK flip-flop with J=K=0
(b) a JK flip-flop with J=K=1
(c) a D flip-flop with D=0
(d) an SR latch with S=R=1

Q6. Setup time is the interval during which the data input must be stable:

(a) after the active clock edge
(b) before the active clock edge
(c) during clock-to-Q delay
(d) between two clock edges

Q7. Clock-to-Q delay ( $t_{CQ}$ ) refers to:

(a) time for the clock to reach the flip-flop
(b) delay from the active clock edge to a valid output
(c) time data must be stable before the edge
(d) propagation through combinational logic

Q8. A 4-bit ripple (asynchronous) counter differs from a synchronous counter because:

(a) it uses no flip-flops
(b) each flip-flop is clocked by the previous stage's output
(c) all flip-flops share the same clock
(d) it counts only in binary-coded decimal

Q9. An $n$ -bit Johnson (twisted-ring) counter has how many unique states in its normal cycle?

(a) $n$
(b) $2n$
(c) $2^n$
(d) $n^2$

Q10. The defining characteristic of a Mealy finite state machine is that its outputs depend on:

(a) the present state only
(b) the present state and current inputs
(c) the next state only
(d) the clock frequency only

Q11. Metastability in a flip-flop is best described as:

(a) a permanent stuck-at fault
(b) an unresolved intermediate output state that may persist unpredictably
(c) normal toggling behavior
(d) a state with zero power consumption

Q12. A common technique to safely pass a single-bit signal across two clock domains is:

(a) a two-flip-flop synchronizer
(b) a ripple counter
(c) a NOR latch
(d) reducing the supply voltage

Section B — Matching (5 marks total, 1 each)

Q13. Match each device/term (i–v) to its correct description (A–E).

#	Term		Description
i	Ring counter	A	Outputs depend on present state only
ii	Moore machine	B	Single '1' circulates among flip-flops
iii	T flip-flop	C	Difference in clock arrival times at different FFs
iv	Clock skew	D	Toggles output when input is asserted
v	Shift register	E	Moves stored bits one position per clock

Section C — True/False with Justification (2 marks each)

Q14. True or False: A synchronous counter generally has lower maximum operating frequency than an asynchronous ripple counter of the same size. Justify.

Q15. True or False: Clock jitter is a static (fixed) offset between clock edges at two flip-flops. Justify.

Q16. True or False: State minimization can reduce the number of flip-flops required to implement an FSM. Justify.

Q17. True or False: In a Moore machine, an input change can cause the output to change immediately, before the next clock edge. Justify.

Q18. True or False: Violating the hold-time constraint can be fixed by simply lowering the clock frequency. Justify.

Q19. True or False: A two-stage synchronizer completely eliminates the possibility of metastability. Justify.

Answer keyMark scheme & solutions

Section A (1 mark each)

Q1 — (d) S=1, R=1. In a NOR-based SR latch, S=R=1 forces both outputs to 0, violating the Q/Q̄ complement relationship; the subsequent state is unpredictable when both return to 0. (1)

Q2 — (b) enable signal is active. A gated (level-sensitive) D latch passes D to Q whenever enable is asserted — this is transparency. (1)

Q3 — (a) latch is level-sensitive, flip-flop is edge-sensitive. The latch follows input while enable is high; the flip-flop captures only at the clock edge. (1)

Q4 — (d) toggle. J=K=1 is the toggle condition for a JK flip-flop. (1)

Q5 — (b) JK with J=K=1. T=1 toggling equals JK toggle mode. (1)

Q6 — (b) before the active clock edge. Setup time = data-stable window before the edge. (1)

Q7 — (b) delay from active clock edge to valid output. Definition of $t_{CQ}$ . (1)

Q8 — (b) each FF clocked by previous stage's output. Ripple counters chain clocks; synchronous ones share one clock. (1)

Q9 — (b) $2n$ . A Johnson counter produces $2n$ unique states (vs. $n$ for a ring counter). (1)

Q10 — (b) present state and current inputs. That is the Mealy definition. (1)

Q11 — (b) unresolved intermediate state that may persist unpredictably. Metastability occurs on setup/hold violation. (1)

Q12 — (a) two-flip-flop synchronizer. Standard single-bit CDC technique. (1)

Section B (1 mark each)

Q13:

i → B (Ring counter: single '1' circulates)
ii → A (Moore: output depends on state only)
iii → D (T flip-flop: toggles when asserted)
iv → C (Clock skew: difference in clock arrival times)
v → E (Shift register: shifts bits one position/clock)

(1 mark per correct pair, total 5)

Section C (2 marks each: 1 verdict + 1 justification)

Q14 — FALSE. (1) Justification: In a ripple counter, clock propagates through each stage, so delays accumulate, limiting speed; a synchronous counter clocks all FFs simultaneously and is generally faster. (1)

Q15 — FALSE. (1) Justification: Jitter is the random/time-varying deviation of a clock edge from its ideal position. A fixed spatial offset between two FFs' clock edges is skew, not jitter. (1)

Q16 — TRUE. (1) Justification: Merging equivalent states reduces total states; since flip-flops needed = $\lceil \log_2(\text{states}) \rceil$ , fewer states can reduce the count. (1)

Q17 — FALSE. (1) Justification: In a Moore machine outputs depend only on the present state, which changes only at the clock edge; inputs cannot directly/immediately alter the output (that is Mealy behavior). (1)

Q18 — FALSE. (1) Justification: Hold-time violations depend on the data-path minimum delay after the edge, independent of clock period; lowering frequency does not help. (Setup violations are fixed by slowing the clock; hold requires adding delay/buffers.) (1)

Q19 — FALSE. (1) Justification: A synchronizer only reduces the probability (raises MTBF) that metastability propagates; it cannot make the probability exactly zero. (1)

[
  {"claim":"Johnson counter with n=4 flip-flops has 2n = 8 unique states","code":"n=4; result = (2*n == 8)"},
  {"claim":"Ring counter (n states) has fewer states than Johnson counter (2n) for n>0","code":"n=4; result = (n < 2*n)"},
  {"claim":"Flip-flops needed for an FSM with 5 states is ceil(log2(5)) = 3","code":"import math; result = (math.ceil(math.log(5,2)) == 3)"},
  {"claim":"Minimizing 8 states to 4 states reduces FF count from 3 to 2","code":"import math; before=math.ceil(math.log(8,2)); after=math.ceil(math.log(4,2)); result = (before==3 and after==2)"}
]