Sequential Circuits

Q1. (3 marks)

• Definition: An SR latch is a bistable memory element with two inputs, Set (S) and Reset (R), that stores one bit; S=1 sets Q=1, R=1 resets Q=0. (1 mark)
• Forbidden input: For a NOR-based SR latch, $S=R=1$ is forbidden. (1 mark)
• Why: With both inputs high, both outputs are forced to 0, so $Q$ and $\bar Q$ are no longer complementary; and on releasing both inputs simultaneously the final state is unpredictable (race condition). (1 mark)

Q2. (4 marks)

• When $E=1$ (transparent): $Q_{next}=D$. (2 marks)
• When $E=0$ (hold/latched): $Q_{next}=Q$ (retains previous value). (2 marks)

Q3. (4 marks)

• (a) JK: $Q_{next}=J\bar Q + \bar K Q$. (2 marks)
• (b) T: $Q_{next}=T\oplus Q = T\bar Q + \bar T Q$. (1 mark)
• (c) D: $Q_{next}=D$. (1 mark)

Q4. (5 marks)

• Setup time $t_{su}$: minimum time the data input must be stable before the active clock edge. (1 mark)
• Hold time $t_h$: minimum time the data input must remain stable after the active clock edge. (1 mark)
• Max frequency: The clock period must satisfy $T \ge t_{cq}+t_{logic}+t_{su}=0.4+2.1+0.3=2.8\text{ ns}.$ (2 marks)
• $f_{max}=1/T = 1/2.8\text{ ns}\approx 357.1\text{ MHz}.$ (1 mark)

Q5. (4 marks)

• Synchronous: all flip-flops share a common clock; they change state simultaneously. (1 mark)
• Asynchronous (ripple): clock of each stage is driven by the output of the previous stage; state changes ripple through. (1 mark)
• Advantage of synchronous: no cumulative propagation delay → faster, glitch-free, higher max frequency. (1 mark)
• Advantage of asynchronous: simpler circuit, fewer gates, lower power/hardware cost. (1 mark)

Q6. (5 marks)

• (a) 4-bit ring counter: 4 distinct states. 4-bit Johnson counter: 8 distinct states ($2n$). (2 marks: 1 each)
• (b) Johnson counter from $0000$ (shift with inverted feedback): (3 marks)
  • $0000 \to 1000 \to 1100 \to 1110$

Q7. (4 marks)

• Mealy machine: output depends on both the current state and the current inputs. (1.5 marks)
• Moore machine: output depends only on the current state. (1.5 marks)
• The Moore machine is the one whose output depends only on the current state. (1 mark)

Q8. (5 marks) For a T flip-flop, $T = Q_{next}\oplus Q_{present}$. Counting $0\to1\to2\to3\to0$:

(3 marks for correct table)

• $T_0=1$ always (LSB toggles every count). (1 mark)
• $T_1=Q_0$ (MSB toggles when LSB is 1). (1 mark)

Q9. (3 marks)

• Metastability: an unstable intermediate condition where a flip-flop's output hovers between valid logic 0 and 1 for an unbounded time, occurring when setup/hold timing is violated (e.g., asynchronous input). (2 marks)
• Two-FF synchroniser: the first flip-flop may go metastable, but the extra clock period before the second flip-flop samples gives the metastable state time to resolve, greatly reducing the probability of propagating an invalid value downstream. (1 mark)

Q10. (3 marks)

• Clock skew: the spatial difference in clock arrival time at different flip-flops caused by unequal routing/distribution paths (a fixed/static offset). (1.5 marks)
• Clock jitter: the temporal variation of the clock edge from its ideal position from cycle to cycle (a random/dynamic timing uncertainty). (1.5 marks)

[
  {"claim":"Min clock period is 2.8 ns", "code":"tcq=Rational(4,10); tlogic=Rational(21,10); tsu=Rational(3,10); T=tcq+tlogic+tsu; result = (T == Rational(28,10))"},
  {"claim":"f_max approx 357.1 MHz", "code":"T=Rational(28,10); f=1/(T*10**-9); result = (round(f/10**6,1)==357.1)"},
  {"claim":"Johnson counter 4-bit has 8 states, ring has 4", "code":"n=4; result = (2*n==8 and n==4)"},
  {"claim":"T flip-flop inputs: T0 always 1, T1 = Q0 for 2-bit up counter", "code":"states=[(0,0),(0,1),(1,0),(1,1)]; ok=True\nfor i,(q1,q0) in enumerate(states):\n    n1,n0=states[(i+1)%4]\n    T1=q1^n1; T0=q0^n0\n    if T0!=1 or T1!=q0: ok=False\nresult = ok"}
]