Clock-to-Q delay

3.4.6 · Hardware › Sequential Circuits

Yeh hai kya

Manufacturers actually do numbers dete hain:

Yeh kyun matter karta hai: timing equation (scratch se derive ki gayi)

Socho do flip-flops ke beech combinational logic ka ek block hai, sab ek hi clock share kar rahe hain.

Har cycle mein signal kaise travel karta hai:

Clock edge FF1 ko hit karti hai → $t_{p c q}$ ke baad, FF1 ka output $Q_{1}$ valid ho jaata hai.
$Q_{1}$ combinational logic se guzarta hai → $t_{p d}$ (logic propagation delay) ke baad, FF2 ka input valid ho jaata hai.
FF2 ko apna input apni clock edge se pehle stable chahiye, setup time $t_{se t u p}$ ke barabar.

Data ko agli edge (ek period $T_{c}$ baad) ke liye time par pahunchne ke liye:

$FF1 launch karta hai t_{p c q} + logic t_{p d} + FF2 catch karta hai t_{se t u p} \leq T_{c}$

Aur hold side (fast delay $t_{cc q}$ use karke):

Common mistakes

Recall Feynman: 12-year-old ko explain karo

Socho ek relay race. Jab starting whistle bajti hai (clock edge), runner (flip-flop) teleport nahi karta — react karne mein aur daudna shuru karne mein thoda time lagta hai. Woh reaction moment clock-to-Q delay hai. Puri lap (ek clock tick) itni lambi honi chahiye ki yeh reaction fit ho sake, plus daudna (logic), plus agla runner baton pakdne ke liye tayaar ho (setup). Agar lap zyada chhoti ho, koi baton drop kar deta hai — circuit galat answers deta hai.

Active recall

Clock-to-Q delay

t_{c q}

kya hai?

Active clock edge se us time tak ka duration jab tak output

Q

valid aur stable ho jaata hai.

Setup / max-frequency check kaun si delay use karta hai, min ya max?

Maximum (

t_{p c q}

), propagation clock-to-Q delay (worst case).

Hold check kaun si delay use karta hai?

Minimum (

t_{cc q}

), contamination clock-to-Q delay (jaldi se jaldi Q change hota hai).

Minimum clock period inequality likho.

T_{c} \geq t_{p c q} + t_{p d} + t_{se t u p}

Hold-time constraint likho.

t_{cc q} + t_{p d, m i n} \geq t_{h o l d}

Q clock edge par instantly kyun nahi badalta?

Internal transistor capacitances ko charge/discharge karna hota hai, jo physical time leta hai.

Hold violation ko kaise fix karte hain?

Chhote combinational path mein delay (buffers) add karo taaki data itni der baad aaye.

t_{p c q} = 30

ps,

t_{p d} = 100

ps,

t_{se t u p} = 20

ps →

f_{ma x}

1/150 ps \approx 6.67

GHz.

t_{cc q}

aur

t_{p c q}

ka relation kya hai?

t_{cc q} \leq t_{p c q}

(contamination ≤ propagation).

Connections

Setup and Hold Time — baaki do timing parameters; $t_{c q}$ unke saath kaam karta hai.
Flip-Flops — woh device jiska output delay yeh describe karta hai.
Combinational Logic Delay — equation mein $t_{p d}$ term.
Maximum Clock Frequency — $t_{c q}$ use karke directly derive hoti hai.
Timing Analysis — setup/hold/clock-to-Q ka overall framework.
Clock Skew — jab clock alag-alag times par aati hai toh yeh equations modify ho jaati hain.