Registers and shift registers

A register is just a row of flip-flops that remember bits together. A shift register additionally moves those bits sideways on each clock. Everything below is built up from a single D flip-flop.

Starting point: the D flip-flop

1. The Register (parallel load)

HOW it works (derivation from the atom): Take $n$ D flip-flops. Wire all their clocks together. Give each its own $D_i$ and read each $Q_i$ . $Q_i^{\text{next}} = D_i \quad \text{for } i = 0,1,\dots,n-1$ At the edge, all $D_i \to Q_i$ at once → the whole word is captured in one clock tick.

Adding a Load-Enable (why we need control)

A plain register grabs $D$ every edge. Usually we want it to hold until told to load.

Derivation: we want $Q^{\text{next}} = \begin{cases} D & \text{if } LOAD = 1 \\ Q & \text{if } LOAD = 0 \end{cases}$ Build the flip-flop input using a 2-to-1 mux fed by $LOAD$ : $D_{\text{ff}} = LOAD \cdot D + \overline{LOAD}\cdot Q$ When $LOAD=0$ , the flip-flop feeds its own output back → it remembers. This is exactly how a CPU register only updates when the instruction says so.

2. The Shift Register

Derivation from the atom: instead of giving flip-flop $i$ its own external $D_i$ , feed it the previous flip-flop's output: $D_i = Q_{i-1}$ . Then at each edge the pattern slides one position; a fresh bit enters at one end, the far bit falls out as Serial Out.

The four classic types (WHAT combinations exist)

Data can go in serially or in parallel, and come out serially or in parallel:

Type	In	Out	Use
SISO	Serial	Serial	delay line / time buffer
SIPO	Serial	Parallel	receive serial data, read as word
PISO	Parallel	Serial	transmit a word one bit at a time
PIPO	Parallel	Parallel	it's just a register with routing

Timing intuition (Forecast-then-Verify)

For an $n$ -bit SISO shift register, a bit that enters now appears at the output after $n$ clock edges — one edge per stage.

Worked Examples

Clock	$Q_3Q_2Q_1Q_0$	Why this step?
start	1011	initial
1	0101	each bit moves right one place; MSB←0
2	0010	again slide right; the trailing 1 is dropped
3	0001	value halved each shift: 11→5→2→1

Why? Right shift by 1 = integer divide by 2. $11 \to 5 \to 2 \to 1$ ✔ (matches truncated division).

Clock	Serial In	$Q_3Q_2Q_1Q_0$	Why this step?
0	–	0000	cleared
1	1	0001	first bit lands in $Q_0$
2	0	0010	old bit shifts up, new 0 enters
3	1	0101	keep marching
4	1	1011	full word assembled → read in parallel

Why? After 4 clocks the 4 serial bits are sitting as one parallel word $1011$ — that's serial→parallel conversion.

Common Mistakes

Active Recall

Recall Explain to a 12-year-old (Feynman)

Imagine a line of kids each holding one card. A register is when, on a whistle, every kid gets handed a new card at the same time — they now remember a whole hand together. A shift register is when, on each whistle, every kid passes their card to the kid on their right, and a new card is handed to the kid on the far left. After enough whistles, the card you put in at one end walks all the way to the other end and falls off. Passing cards one step = the number gets doubled or halved, and passing cards one-by-one lets you send a whole hand down a single narrow hallway.

Flashcards

What is a register?

A set of

n

D flip-flops on a common clock storing an

n

-bit word, loaded in parallel.

What makes a register a shift register?

Each flip-flop's D input is fed by the previous flip-flop's output (

D_i=Q_{i-1}

), so bits move one position per clock.

Why must all flip-flops in a register share one clock?

So all bits update simultaneously (atomically), avoiding glitch/mixed-state words.

Equation for a register with load-enable?

D_{ff}=LOAD\cdot D+\overline{LOAD}\cdot Q

; loads

D

when LOAD=1, holds when LOAD=0.

What arithmetic operation does a left shift perform?

Multiply by 2 (each bit moves to a higher power-of-2 position), if no overflow.

What does an unsigned right shift do numerically?

Floor division by 2 (LSB is discarded).

After how many clocks does a bit traverse an n-bit SISO register?

n clock edges (one per stage).

What are the four shift-register I/O types?

SISO, SIPO, PISO, PIPO (Serial/Parallel In × Serial/Parallel Out).

Which type converts serial data into a parallel word?

SIPO (Serial-In Parallel-Out).

Which type transmits a stored word one bit at a time?

PISO (Parallel-In Serial-Out).

For a signed number, what right shift preserves value?

Arithmetic right shift — copy the sign bit into the MSB.

Connections

D flip-flop — the building atom of every register
Multiplexers — how a load-enable / mode-select is built
Counters — a ring/Johnson counter is a shift register with feedback
Serial communication (UART, SPI) — SIPO/PISO do the packing/unpacking
Binary multiplication and division — shift-and-add uses shift registers
Clocking and setup/hold time — why the common clock must meet timing

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, register ka matlab simple hai: kai saare D flip-flops ko ek saath, ek hi common clock pe laga do. Har flip-flop 1 bit yaad rakhta hai, to 8 flip-flops mil ke ek pura byte (8 bit) store kar lete hain. Common clock isliye zaroori hai taaki saare bits ek saath, ek hi tick pe update hon — warna kabhi aadha purana kabhi aadha naya bit reh jayega aur galat value milegi.

Shift register thoda alag wiring hai. Yahan har flip-flop ka input apne padosi flip-flop ke output se juda hota hai ( $D_i = Q_{i-1}$ ). Iska matlab har clock edge pe data ek step side me khisak jaata hai — ek naya bit ek end se andar aata hai (Serial In), aur dusre end se ek bit bahar gir jaata hai (Serial Out). Kaafi useful cheez hai: ek hi taar pe ek-ek karke bits bhej sakte ho (serial), phir dusri taraf unhe jod ke pura word bana sakte ho (parallel). Isi ko SIPO, PISO waghera kehte hain.

Ek important trick: left shift = ×2, right shift = ÷2. Kyunki binary me har position ek power of 2 hoti hai, bit ko upar khiskao to value double, neeche khiskao to half. Example: 0011 (=3) left shift → 0110 (=6). Bas dhyan rakho — right shift me sabse chhota bit gir jaata hai (floor division), aur signed numbers ke liye sign bit copy karna padta hai (arithmetic shift).

Yaad rakhne wali baat: register me har flip-flop ka apna independent input hota hai (parallel load, koi movement nahi), jabki shift register me input padosi se aata hai (data move karta hai). Confuse mat hona — wiring hi difference create karti hai!

Starting point: the D flip-flop

1. The Register (parallel load)

Adding a Load-Enable (why we need control)

2. The Shift Register

The four classic types (WHAT combinations exist)

Timing intuition (Forecast-then-Verify)

Worked Examples

Common Mistakes

Active Recall

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Sequential Circuits

Connections