Registers and shift registers: Question bank — Hardware deep dive

Before we start, one shared vocabulary so no symbol, abbreviation, or picture is used unexplained:

Definition The words we lean on

A flip-flop is a 1-bit memory cell that copies its input $D$ to its output $Q$ only at the clock edge (the instant the clock line flips 0→1). See D flip-flop.
== $n$ == = the bit-width of the register — how many flip-flops sit side by side. An $n$ -bit register has stages numbered $0$ to $n - 1$ , so $n = 4$ means four flip-flops $Q_{0}, Q_{1}, Q_{2}, Q_{3}$ .
$Q_{i}$ = the output bit of the $i$ -th flip-flop. $Q_{0}$ is usually the LSB (least significant bit, the "ones" place); $Q_{n - 1}$ the MSB (most significant bit, the highest power-of-2 place).
Serial In = the single external wire feeding the first stage. Serial Out = the bit falling off the far end.
"Shift left" here means $Q_{i}^{next} = Q_{i - 1}$ (bits move toward higher indices / higher place value). "Shift right" means $Q_{i}^{next} = Q_{i + 1}$ (toward the LSB).

Two small pictures ground everything on this page — glance at them before the questions.

Figure 1 tells apart the two structures the whole page turns on: a plain register (independent external $D_{i}$ ) versus a shift register (each $D_{i}$ fed by the neighbour $Q_{i - 1}$ , first stage fed by Serial In).

Figure 2 is the timing picture behind every "glitch"/"common clock" question: one shared clock updates all bits atomically, while skewed clocks let a reader catch a half-old, half-new word.

True or false — justify

Is a register just a shift register with the wiring removed?

False — it's the opposite direction of building. A register gives each flip-flop its own external

D_{i}

(Figure 1, left); a shift register replaces that with

D_{i} = Q_{i - 1}

(Figure 1, right). You add the neighbour-wiring to get a shift register, you don't remove wiring from it.

In an

n

-bit SISO (Serial-In Serial-Out) register, does a bit you feed in now appear at the output on the very next clock edge?

False — it appears after ==

n

clock edges==, one per stage. Only in a 1-bit register would "now" and "next edge" coincide.

Does a left shift of an unsigned number always multiply it by 2?

False — only if no bit falls off the MSB. Once the top bit is a 1 and gets shifted out, that's overflow and the value wraps, so

\times 2

fails.

Is an unsigned right shift the same as exact division by 2?

False — it's floor division. The discarded LSB is lost, so

11 \to 5

(not

5.5

); the fractional part is truncated, never rounded.

For a signed number, does shifting a 0 into the MSB on a right shift preserve the value?

False — you must copy the sign bit into the MSB (arithmetic right shift). Shoving in a 0 turns a negative number positive, corrupting the value.

Do all flip-flops in a register need the same clock to work at all?

False for "work at all," true for "work correctly." Separate clocks would still store bits, but bits would update at different instants (Figure 2, bottom), producing a glitchy mixed old/new word. One clock makes the update atomic.

Is PIPO (Parallel-In Parallel-Out) essentially just a register?

True — with parallel load and parallel read and no actual shifting, PIPO is a plain register with routing. The "shift" ability is unused.

Does adding a

L O A D

-enable change what the flip-flop stores between load events?

True in intent, via feedback: when

L O A D = 0

the mux routes

Q

back to

D_{ff}

, so the flip-flop re-loads its own value and appears to "hold." It still samples every edge — it just samples itself. See Multiplexers.

Can a shift register work with an undriven Serial In line?

False — the first stage samples whatever is on that line (Figure 1, right, the red input). Floating/undriven means you shift in garbage bits, corrupting the word after

n

shifts.

Spot the error

"A right shift on

1011

(=11) gives

0101

(=5), so right shift always divides exactly." Find the flaw.

The dropped LSB is the flaw:

11/2 = 5.5

but the register gives

5

. It's floor division; the "exactly" is wrong because the fraction is silently discarded.

"To send a stored byte over one wire, I use a SIPO shift register." Spot the mistake.

Wrong type. Sending a stored word out one wire is PISO (Parallel-In Serial-Out). SIPO (Serial-In Parallel-Out) does the reverse — it receives a serial stream and lets you read it in parallel. See Serial communication (UART, SPI).

"I wired each flip-flop's clock separately so they'd be independent — cleaner design." What breaks?

Independence is exactly the bug. With separate (skewed) clocks the

n

bits update at slightly different times (Figure 2, bottom), so a reader can catch a half-old, half-new word (a glitch). The whole point of a register is one common clock. See Clocking and setup/hold time.

"Left shift multiplies by 2, so shifting

1100

(=12) left gives 24 =

11000

." Spot the error in a 4-bit register.

In only 4 bits (

n = 4

) there is no fifth position — the MSB 1 falls off. You get

1000

(=8), not 24. This is overflow; the

\times 2

rule holds only when the top bit is 0 before the shift.

"In a shift register, if I set all

D_{i} = Q_{i - 1}

then

Q_{0}

takes care of itself." What's missing?

Q_{0}

has no "previous" flip-flop, so

D_{0}

is undefined by that rule.

Q_{0}^{next}

must come from the external Serial In (Figure 1, right). Forgetting to drive it is the classic trap.

"A ring counter and a plain shift register are unrelated circuits." Correct it.

They're closely related: a ring counter is a shift register with its Serial Out fed back into Serial In. The feedback is the only added wire. See Counters.

Why questions

Why does one common clock prevent glitches rather than cause them?

Because every flip-flop samples at the same instant (Figure 2, top), the whole word transitions from fully-old to fully-new in one edge — there is no in-between moment where bits disagree.

Why does each left-shift multiply a binary number by 2?

Every bit moves to the next higher position, and each position is worth twice the one below it (

2^{k} \to 2^{k + 1}

). Multiplying every place value by 2 multiplies the whole number by 2. See Binary multiplication and division.

Why can't a naive right shift handle negative numbers?

Negative numbers store their sign in the MSB. A right shift that inserts a 0 into that MSB erases the sign, so the number reads as positive. Copying the old sign bit back in (arithmetic shift) keeps the value's sign intact.

Why does a bit take exactly

n

edges to cross an

n

-bit SISO register, not fewer?

Each clock edge moves a bit one stage (follow one bit across Figure 1, right). With

n

stages between input and output, you need

n

separate edges — the register is literally a programmable delay of

n

ticks.

Why do we bother with a

L O A D

-enable instead of loading every edge?

A CPU register must hold a value across many clock cycles and only update when an instruction says so.

L O A D

-enable lets the register ignore edges (hold when

L O A D = 0

) until commanded, using a mux to choose "new data" vs "myself." See Multiplexers.

Why is serial transmission (one wire) worth the extra shift-register hardware?

It trades many parallel wires for time: 8 bits go down one wire over 8 clocks. Fewer wires means cheaper cables, connectors, and PCB routing — the core idea behind UART/SPI. See Serial communication (UART, SPI).

Edge cases

What does a SISO register output on clock edges

1

through

n - 1

, before the first fed bit arrives?

It outputs the pre-existing bits that were already sitting in the last stage (the register's old contents), not the new input — which only reaches the output on edge

n

What happens if Serial In is held constant at 1 forever while shifting?

The register fills up with 1s from the input end; after

n

shifts it becomes all-1s. It's a way to "flood" the register with a known pattern.

What is stored in a freshly powered-on register before any clock edge?

An undefined / arbitrary pattern — flip-flops power up in an unknown state. You must explicitly clear or load a known value before trusting the contents.

Right-shifting the value

0001

(=1) once with Serial In = 0 gives what, and what does it mean?

It gives

0000

(=0). The lone 1 was the LSB, so floor-division

1/2 = 0

— the register has reached its "empty" fixed point.

If you keep shifting a fixed word with Serial In tied to 0, what is the eventual steady state?

All zeros. Every real bit eventually falls off the far end and only 0s are shifted in, so the register drains to

0000

In a shift register that both shifts and can parallel-load, what decides which happens on an edge?

A mode-select line drives a mux at each flip-flop's

D

input: one mode routes

Q_{i - 1}

(shift), the other routes external

D_{i}

(load). The clock edge acts; the mode chooses the source. See Multiplexers.

Active Recall

Recall One-sentence killers for the top 3 traps

(1) Right shift = floor divide, never exact. (2) Left shift = ×2 only if the MSB was 0. (3) A shift register always needs Serial In driven — the first stage has no neighbour to copy.

Connections

Registers and shift registers — parent topic these traps drill
D flip-flop — the 1-bit atom every question rests on
Multiplexers — LOAD-enable and shift/load mode-select
Counters — ring/Johnson counters as shift registers with feedback
Serial communication (UART, SPI) — SIPO/PISO packing and unpacking
Binary multiplication and division — why shifts scale by 2
Clocking and setup/hold time — why the common clock matters