Exercises — Registers and shift registers

Each flip-flop's $D$ is external and independent, and no output loops into a neighbour's input. Data does not move sideways — it is loaded in parallel. So this is a plain register. It stores $8$ bits = 1 byte. The give-away rule: shift register ⟺ $D_i=Q_{i-1}$ (neighbour feeds neighbour). Here that link is absent.

• (a) SIPO (Serial-In Parallel-Out) — used by a UART/SPI receiver.
• (b) PISO (Parallel-In Serial-Out) — the transmitter side.
• (c) SISO (Serial-In Serial-Out) — bit enters, walks the chain, leaves later.
• (d) PIPO (Parallel-In Parallel-Out) — just a register. Mnemonic: read In first, Out second.

Left shift: every bit moves toward the MSB, the top bit $Q_3$ falls off, Serial-In ($=1$) fills $Q_0$.

Answer: $1111$.

"Empty" here means every flip-flop was reset to $0$ before the first edge — otherwise the early Serial-Out bits would be unknown ($X$), and we could not tabulate them. With a known all-zeros start: A bit must cross all $n=5$ stages, so it emerges after 5 edges. The output stream is the input stream delayed by 5 edges. Watching the far-end bit:

The first $1$ appears on edge 5; a SISO of length $n$ is a pure $n$-clock delay. (Had the register started at unknown values, edges 1–4 would read $X$, not $0$.)

$10110100_2=128+32+16+4=180$.

Notice shift 3: $45$ is odd, its LSB ($1$) is dropped, so $45\to 22$ not $22.5$ — that dropped bit is the truncation. This is exactly the "floor" in Binary multiplication and division.

The figure below traces these four rows: green cells are $1$s, and the coral cell marks the LSB that is about to be discarded on the next shift — the visible source of the "floor".

Two's complement of 8 bits: the MSB carries weight $-128$. $11110000_2=-128+64+32+16=-16$. Arithmetic right shift copies the sign bit (1) into the vacated MSB: $11110000\to 11111000_2=-128+64+32+16+8=-8.$ And $-16/2=-8$ ✔ — value halved correctly. Logical right shift (fill 0): $11110000\to 01111000_2=64+32+16+8=+120✗$ Completely wrong sign and magnitude. That's why signed division needs arithmetic shift.

We must keep two names apart: $D_i$ is the input pin of flip-flop $i$ (what the mux drives), while $P_i$ is the external parallel-load data for stage $i$. Each stage's $D_i$ is chosen by a 4-to-1 mux whose select lines are $S_1{S}_0$: $D_i=\overline{S_1}\overline{S_0}{Q}_i+\overline{S_1}{S}_0{Q}_{i+1}+S_1\overline{S_0}{Q}_{i-1}+S_1{S}_0{P}_i$ Input-by-input:

• $S_1{S}_0=00\Rightarrow D_i=Q_i$: the stage feeds itself back → it remembers (same idea as the parent's load-enable).
• $S_1{S}_0=01\Rightarrow D_i=Q_{i+1}$: content of the higher stage flows down → shift right.
• $S_1{S}_0=10\Rightarrow D_i=Q_{i-1}$: content of the lower stage flows up → shift left.
• $S_1{S}_0=11\Rightarrow D_i=P_i$: the external parallel data is captured → parallel load.

One mux per stage, all sharing $S_1{S}_0$ and one clock, gives a fully universal register (hold / shift-R / shift-L / load). This is the classic 74194-style part.

Feedback closes the chain: $Q_0^{next}=Q_3$ instead of an external Serial-In. Left shift each edge ($Q_i^{next}=Q_{i-1}$, $Q_0^{next}=Q_3$). From $1000$ the single 1 wraps to the bottom and walks up:

The single 1 circulates. Period = 4 (equals the number of stages). That's a ring counter: $n$ states from $n$ flip-flops, one-hot encoded.

(a) $0xB3=10110011_2$. Decimal: $128+32+16+2+1=179$. (b) LSB-first means we send $Q_0$ first, up to $Q_7$: bits of $10110011$ from LSB: $1,1,0,0,1,1,0,1$. (c) The SIPO receives LSB-first and shifts each new bit into the MSB end, pushing older bits toward the LSB (so the first-received LSB ends up in $Q_0$). After 8 clocks the receiver holds $10110011=0xB3=179$. ✔ Yes, it matches — a correctly-ordered serial channel is loss-free.

(a) Period $=1/(50\times 10^6\text{Hz})=20\text{ns}$. (b) Setup (the "not too late" check): the data launched at one edge must be stable at the next flip-flop $t_{su}$ before the next edge. Required: $t_{pd}+t_{su}=1.5+0.5=2.0\text{ns}$. Since $2.0\le 20$, there is huge margin (setup slack $=18\text{ns}$) → meets setup. (c) Hold (the "not too early" check): the new data must not arrive so fast that it overruns the current flip-flop's hold window right after the edge. The data can change no sooner than $t_{pd}$ after the edge, so hold is met when $t_{pd}\ge t_h$: here $1.5\ge 0.3$, hold slack $=1.2\text{ns}$ → meets hold. (Hold is a per-edge, clock-frequency-independent check — slowing the clock never fixes a hold violation, which is why we check it separately; see Clocking and setup/hold time.) (d) A bit crosses $16$ stages = $16$ clock edges = $16\times 20\text{ns}=320\text{ns}$. Length worsens latency, never per-edge timing, because each stage only talks to its immediate neighbour.

Q: After how many edges does a bit leave an $n$-stage SISO? ::: $n$ edges (one hop per stage). Q: What single wiring change turns a shift register into a ring counter? ::: Feed $Q_{n-1}$ back into $Q_0$ (close the loop). Q: What fills the MSB in a signed (arithmetic) right shift? ::: A copy of the old sign bit. Q: Which select input of the universal-stage mux gives "hold"? ::: $D_i=Q_i$ (self-feedback), mode $S_1{S}_0=00$. Q: Which timing check is independent of clock frequency? ::: Hold time ($t_{pd}\ge t_h$).