Multiplexers (2 - 1, 4 - 1, n - 1)

WHY do we need a MUX?

WHAT is a multiplexer — the definition

The number of select lines needed for $N$ inputs: since $n$ bits address $2^n$ inputs, $n = \lceil \log_2 N \rceil.$

HOW to derive the Boolean expression (from scratch)

We build the equation the way a decoder does: each input is ANDed with the minterm of the selects that "point at" it", and all these products are ORed.

2:1 MUX derivation

We want $Y = I_0$ when $S=0$ and $Y=I_1$ when $S=1$. "When $S=0$" is captured by the term $\bar S$; "when $S=1$" by $S$. So:

$Y = \bar S\,I_0 + S\,I_1$

4:1 MUX derivation

Two selects $S_1 S_0$ give four minterms. Input $I_k$ is passed when $S_1S_0$ spells $k$:

General n:1 MUX

$\boxed{Y = \sum_{k=0}^{2^n-1} m_k \, I_k}$ where $m_k$ is the minterm of the select variables corresponding to $k$. This sum-of-products is literally a decoder (the minterms) feeding AND–OR logic.

MUX as a universal function generator (the 80/20 gem)

Trick (Shannon expansion): to build an $n$-variable function with a smaller $2^{n-1}:1$ MUX, put $n-1$ variables on selects; each data input becomes one of $\{0, 1, v, \bar v\}$ of the leftover variable $v$.

Enable line

Real MUX chips add an enable $E$. Typically $Y = E\cdot(\text{MUX expression})$ (active-high), so $E=0$ forces $Y=0$ (or high-Z on tri-state parts). Enable lets you cascade and tri-state onto a shared bus.

Common mistakes

Connections

• Decoders — the minterm generator inside every MUX (a MUX = decoder + OR).
• Demultiplexers — the exact inverse operation (one to many).
• Boolean Algebra Minterms — the SOP form we derived.
• Shannon Expansion — how to shrink functions onto smaller MUXes.
• Tri-state Buffers — enable line and bus sharing.
• Combinational Logic Design — MUX as universal function block.

Flashcards

Concept Map

Hinglish (regional understanding)