Pass-transistor logic

Chapter: CMOS Circuit Design · Subtopic 3.2.10

The Big Picture

WHAT is a pass transistor?

• Static CMOS gate output: node is pulled to a rail through a transistor.
• PTL: node receives the actual input voltage copied through a conducting channel.

WHY nMOS passes a weak '1' (the central fact)

An nMOS transistor conducts (is ON) only while

$V_{GS} = V_G - V_S > V_{tn}$

HOW this bites us when passing a '1':

Suppose gate is tied to $V_{DD}$ and we apply input $V_{DD}$ at the source, trying to charge an output node (initially 0) up toward '1'. Call the output node voltage $V_{out}$; it acts as the source of the nMOS (current flows out of it into the load).

WHY nMOS passes a perfect '0': discharging toward 0, the source is the low node, $V_S\to 0$, so $V_{GS}=V_{DD}-0=V_{DD}\gg V_{tn}$ — the device stays strongly ON all the way to 0 V. So:

• nMOS: strong 0, weak 1
• pMOS (symmetric argument): strong 1, weak 0 (it stops when $V_{out}$ falls to $|V_{tp}|$).

HOW we fix the weak '1'

1. Transmission gate (CMOS pass gate). Put an nMOS in parallel with a pMOS, driven by complementary gate signals.

2. Level-restoring (swing-restoring) pMOS. After a chain of nMOS pass transistors feeding an inverter, add a feedback pMOS from $V_{DD}$ to the degraded node. When the inverter output goes low, the pMOS pulls the weak-'1' node fully to $V_{DD}$, restoring the level.

Worked Example 1 — 2:1 MUX in PTL

Function: $Y = S\cdot A + \bar S\cdot B$.

Build: one nMOS with gate $S$ passing $A$; one nMOS with gate $\bar S$ passing $B$; drains tied to $Y$.

• Why this step? Exactly one select line is high, so exactly one pass transistor is ON, steering the chosen input to $Y$. Only 2 transistors (+ inverter for $\bar S$) vs. many for full CMOS.

Check $S=1,\,A=1$: the $A$-path nMOS is ON, gate at $V_{DD}$, passing a '1' → output degrades to $V_{DD}-V_{tn}$.

• Why care? If $Y$ drives another gate, that weak '1' may not fully turn off the next pMOS → static leakage. Fix with a transmission gate or restoring inverter.

Worked Example 2 — XOR steering

$Y = A\oplus B$. Use $A$ and $\bar A$ as pass signals steered by $B,\bar B$: $Y = \bar B\cdot A + B\cdot \bar A.$

• Why this step? PTL lets us pass variables themselves (not just rails), so $A$ and $\bar A$ become the data being routed — impossible in pure pull-up/pull-down CMOS thinking. XOR becomes a tiny MUX.

Worked Example 3 — voltage numbers

Let $V_{DD}=1.8$ V, $V_{tn0}=0.4$ V, ignore body effect.

• Weak '1' out of a single nMOS $=1.8-0.4=1.4$ V. Why: conduction stops at $V_{GS}=V_{tn}$.
• Feed a following CMOS inverter with $V_{tp}=-0.4$ V: its pMOS needs $V_{SG}>0.4$, i.e. gate below $1.8-0.4=1.4$ V. Input is exactly $1.4$ V → pMOS is right at threshold, barely off, leaks. Why fix matters: static power ∝ this leakage.

80/20 — the 20% you must own

1. nMOS = strong 0, weak 1 ($V_{DD}-V_{tn}$); pMOS = strong 1, weak 0.
2. Reason: conduction needs $V_{GS}>V_{tn}$, and the passed node is the source.
3. Fix weak levels with a transmission gate or a restoring pMOS.
4. PTL trades transistor count for level degradation + no drive.

Flashcards

Connections

• CMOS Inverter — the load that reveals weak-'1' leakage
• Transmission Gate — the standard PTL fix
• Static CMOS Logic — contrast: pull-up/pull-down vs signal steering
• Threshold Voltage & Body Effect — source of the threshold drop
• Multiplexers — killer app of PTL
• Dynamic Power vs Static Leakage — cost of degraded levels

Concept Map

Hinglish (regional understanding)