Level 2 — RecallCMOS Circuit Design

CMOS Circuit Design

⏱ 30 minutes40 marksprintable — key stays hidden on paper

Difficulty: Level 2 (Recall — definitions, standard problems, short derivations) Time Limit: 30 minutes Total Marks: 40

Instructions: Answer all questions. Show working where required. Use $...$ notation for symbolic answers.

Q1. [4 marks] Describe the structure of a CMOS inverter. State which transistor forms the pull-up network and which forms the pull-down network, and explain what happens at the output when the input is (a) logic 0 and (b) logic 1.

Q2. [4 marks] For a CMOS logic gate implementing a function $F$ , state the two rules relating the pull-up network (PUN, PMOS) and the pull-down network (PDN, NMOS): (a) In terms of series/parallel duality. (b) In terms of which network conducts for output HIGH vs output LOW.

Q3. [5 marks] Design a 2-input CMOS NOR gate. Draw (describe) the transistor arrangement of the pull-up and pull-down networks and give the number of transistors used. Write the Boolean output expression.

Q4. [5 marks] A CMOS gate has supply voltage $V_{DD} = 1.8\ \text{V}$ , total switched load capacitance $C_L = 50\ \text{fF}$ , switching activity factor $\alpha = 0.2$ , and clock frequency $f = 500\ \text{MHz}$ . Calculate the dynamic power dissipation using $P_{dyn} = \alpha C_L V_{DD}^2 f$ .

Q5. [4 marks] Define the four VTC voltage points $V_{OH}$ , $V_{OL}$ , $V_{IH}$ , $V_{IL}$ . State how $V_{IH}$ and $V_{IL}$ are identified on the voltage transfer characteristic.

Q6. [5 marks] For a logic gate the following levels are measured: $V_{OH} = 1.7\ \text{V}$ , $V_{OL} = 0.1\ \text{V}$ , $V_{IH} = 1.0\ \text{V}$ , $V_{IL} = 0.6\ \text{V}$ . Compute the high noise margin $NM_H$ and the low noise margin $NM_L$ . State which margin is smaller.

Q7. [3 marks] Define propagation delay $t_p$ in terms of $t_{pHL}$ and $t_{pLH}$ . State the reference voltage point (in terms of the swing) used to measure these delays.

Q8. [4 marks] Explain the difference between a transmission gate and a single NMOS pass transistor. State one advantage the transmission gate provides for passing a strong logic '1'.

Q9. [3 marks] Explain the operation of dynamic CMOS logic during the precharge and evaluate phases. State the role of the clock signal.

Q10. [3 marks] Define the power-delay product (PDP) and state its physical significance (units and what it represents). Given $P = 20\ \mu\text{W}$ and $t_p = 40\ \text{ps}$ , compute the PDP.

END OF PAPER

Answer keyMark scheme & solutions

Q1. [4 marks]

CMOS inverter = one PMOS (source to $V_{DD}$ ) and one NMOS (source to GND), gates tied together to input, drains tied together to output. (1)
PMOS forms the pull-up network; NMOS forms the pull-down network. (1)
(a) Input = 0: PMOS ON, NMOS OFF → output pulled to $V_{DD}$ = logic 1. (1)
(b) Input = 1: PMOS OFF, NMOS ON → output pulled to GND = logic 0. (1) Why: complementary conduction gives full rail-to-rail output with no static current path.

Q2. [4 marks]

(a) The PUN and PDN are dual networks: series transistors in one correspond to parallel in the other and vice versa. (2)
(b) PUN (PMOS) conducts to pull output HIGH (when $F=1$ ); PDN (NMOS) conducts to pull output LOW (when $F=0$ ). Exactly one network conducts at a time. (2)

Q3. [5 marks]

Function: $F = \overline{A + B}$ . (1)
PDN: two NMOS in parallel (each with gate A, B) between output and GND. (1)
PUN: two PMOS in series (gates A, B) between $V_{DD}$ and output. (1)
Total transistors = 4. (1)
Output expression $F = \overline{A+B}$ (NOR). (1) Why: NOR pulls low if A OR B high → parallel NMOS; dual gives series PMOS.

Q4. [5 marks]

$P_{dyn} = \alpha C_L V_{DD}^2 f$ (1)
$= 0.2 \times 50\times10^{-15} \times (1.8)^2 \times 500\times10^{6}$ (2)
$(1.8)^2 = 3.24$ ; $0.2 \times 50\text{f} = 10\text{fF}$ ; $10^{-14}\times3.24 = 3.24\times10^{-14}$ ; $\times 5\times10^{8} = 1.62\times10^{-5}$ W (1)
$P_{dyn} = 16.2\ \mu\text{W}$ (1)

Q5. [4 marks]

$V_{OH}$ = output high voltage (nominal max output). (0.5)
$V_{OL}$ = output low voltage (nominal min output). (0.5)
$V_{IH}$ = minimum input recognized as logic 1. (0.5)
$V_{IL}$ = maximum input recognized as logic 0. (0.5)
On the VTC, $V_{IL}$ and $V_{IH}$ are the input voltages where the slope $dV_{out}/dV_{in} = -1$ . (2)

Q6. [5 marks]

$NM_H = V_{OH} - V_{IH} = 1.7 - 1.0 = 0.7\ \text{V}$ (2)
$NM_L = V_{IL} - V_{OL} = 0.6 - 0.1 = 0.5\ \text{V}$ (2)
$NM_L (0.5\text{V}) < NM_H (0.7\text{V})$ → low noise margin is smaller. (1)

Q7. [3 marks]

$t_p = \dfrac{t_{pHL} + t_{pLH}}{2}$ (2)
Delays measured at the 50% point of the voltage swing ( $V_{DD}/2$ ) between input and output transitions. (1)

Q8. [4 marks]

Pass transistor = single NMOS (or PMOS); transmission gate = parallel NMOS + PMOS with complementary gate signals. (2)
NMOS passes a weak '1' (degraded to $V_{DD}-V_{tn}$ ); PMOS passes a strong '1'. (1)
The parallel PMOS in the transmission gate restores the full $V_{DD}$ level for logic '1' (and NMOS gives strong '0'), avoiding threshold-drop degradation. (1)

Q9. [3 marks]

Precharge (clock low): PMOS precharges output node to $V_{DD}$ ; evaluate NMOS off. (1)
Evaluate (clock high): precharge PMOS off, foot NMOS on; PDN conditionally discharges the output based on inputs. (1)
Clock controls the two phases and ensures inputs are stable before evaluation (avoids false discharge). (1)

Q10. [3 marks]

PDP = $P \times t_p$ ; energy consumed per switching operation, units of joules (energy). (1.5)
$= 20\times10^{-6} \times 40\times10^{-12} = 8\times10^{-16}\ \text{J} = 0.8\ \text{fJ}$ (1.5)

[
  {"claim":"Q4 dynamic power = 16.2 uW","code":"alpha=Rational(2,10); CL=50e-15; VDD=1.8; f=500e6; P=alpha*CL*VDD**2*f; result = abs(float(P)-16.2e-6) < 1e-9"},
  {"claim":"Q6 NMH=0.7 and NML=0.5, NML smaller","code":"NMH=1.7-1.0; NML=0.6-0.1; result = (abs(NMH-0.7)<1e-9) and (abs(NML-0.5)<1e-9) and (NML<NMH)"},
  {"claim":"Q10 PDP = 0.8 fJ","code":"P=20e-6; tp=40e-12; PDP=P*tp; result = abs(PDP-0.8e-15) < 1e-18"},
  {"claim":"Q3 NOR gate uses 4 transistors","code":"pdn=2; pun=2; result = (pdn+pun)==4"}
]