Level 1 — RecognitionCMOS Circuit Design

CMOS Circuit Design

⏱ 20 minutes30 marksprintable — key stays hidden on paper

Chapter: 3.2 CMOS Circuit Design Level: 1 — Recognition (MCQ, Matching, True/False with justification) Time Limit: 20 minutes Total Marks: 30

Section A — Multiple Choice (1 mark each) — 10 marks

Select the single best answer.

Q1. In a static CMOS inverter, when the input is logic HIGH (V_DD), the output is pulled LOW through:

(a) the PMOS transistor
(b) the NMOS transistor
(c) both transistors
(d) neither transistor

Q2. The pull-up network in a static CMOS gate is built from:

(a) NMOS transistors only
(b) PMOS transistors only
(c) resistors
(d) transmission gates only

Q3. For a 2-input CMOS NAND gate, the pull-down network consists of:

(a) two NMOS transistors in parallel
(b) two NMOS transistors in series
(c) two PMOS transistors in series
(d) two PMOS transistors in parallel

Q4. The dominant component of dynamic power dissipation in CMOS is:

(a) subthreshold leakage
(b) $C_L V_{DD}^2 f$ switching power
(c) gate tunneling
(d) reverse-bias junction leakage

Q5. The high noise margin $NM_H$ is defined as:

(a) $V_{OH} - V_{IH}$
(b) $V_{IL} - V_{OL}$
(c) $V_{OH} - V_{IL}$
(d) $V_{IH} - V_{IL}$

Q6. In the VTC of an inverter, $V_{IL}$ and $V_{IH}$ are the input voltages where the slope equals:

(a) $0$
(b) $+1$
(c) $-1$
(d) $\infty$

Q7. A CMOS transmission gate is formed by:

(a) one NMOS in series with a resistor
(b) an NMOS and a PMOS in parallel with complementary gate signals
(c) two NMOS in series
(d) a PMOS driving an NMOS gate

Q8. A key disadvantage of passing a logic HIGH through a single NMOS pass transistor is:

(a) it passes a degraded HIGH of $V_{DD} - V_{Tn}$
(b) it cannot conduct at all
(c) it consumes constant static power
(d) it inverts the signal

Q9. In dynamic CMOS logic, the output node is charged during the:

(a) evaluate phase
(b) precharge phase
(c) hold phase
(d) reset-to-zero phase

Q10. The power-delay product (PDP) represents:

(a) power divided by delay
(b) energy consumed per switching operation
(c) delay divided by power
(d) static leakage current

Section B — Matching (1 mark each) — 8 marks

Match each term in Column X to its correct description in Column Y. Write pairs like Q11 → (iii).

Column X	Column Y
Q11. Domino logic	(i) Ratio of switching to non-switching output states affecting delay
Q12. Fan-out	(ii) Dynamic gate followed by a static inverter to allow cascading
Q13. Propagation delay $t_p$	(iii) Number of gate inputs a gate output can drive
Q14. Static power	(iv) Time from input transition (50%) to output transition (50%)
Q15. Pull-down network	(v) Power dissipated due to leakage with no switching
Q16. NOR gate PUN	(vi) NMOS transistors that connect output to ground
Q17. Rise time $t_r$	(vii) Two PMOS transistors in series
Q18. Fan-in	(viii) Time for output to go from 10% to 90% of $V_{DD}$

(Column Y has 8 items; Column X item Q18 "Fan-in" maps to a description — use the best remaining fit.)

Section C — True/False WITH Justification (2 marks each) — 12 marks

State True or False (½ mark) and give a one-line justification (1½ marks).

Q19. "An ideal static CMOS gate dissipates zero static power because there is never a direct current path from $V_{DD}$ to ground in a stable logic state."

Q20. "A CMOS NOR gate uses PMOS transistors in parallel for its pull-up network."

Q21. "Increasing the load capacitance $C_L$ reduces the propagation delay of a CMOS gate."

Q22. "A transmission gate passes both strong logic HIGH and strong logic LOW without threshold degradation."

Q23. "In domino logic, only non-inverting logic functions can be implemented directly without additional inverting stages."

Q24. "The power-delay product can be reduced by lowering the supply voltage, since dynamic energy scales with $V_{DD}^2$ ."

Answer keyMark scheme & solutions

Section A (1 mark each)

Q1 — (b) the NMOS transistor. Input HIGH turns NMOS ON (pull-down) and PMOS OFF, so output discharges to ground through NMOS. (1)

Q2 — (b) PMOS transistors only. The pull-up network connects output to $V_{DD}$ using PMOS devices which pass a strong HIGH. (1)

Q3 — (b) two NMOS transistors in series. NAND is LOW only when all inputs HIGH ⇒ series NMOS pull-down; PUN is parallel PMOS. (1)

Q4 — (b) $C_L V_{DD}^2 f$ switching power. Charging/discharging load capacitance dominates dynamic power. (1)

Q5 — (a) $V_{OH} - V_{IH}$ . $NM_H = V_{OH} - V_{IH}$ (margin against noise on a HIGH output). (1)

Q6 — (c) $-1$ . $V_{IL}$ and $V_{IH}$ are defined at unity-gain points where $dV_{out}/dV_{in} = -1$ . (1)

Q7 — (b) NMOS and PMOS in parallel with complementary gates. This gives full-swing bidirectional switch. (1)

Q8 — (a) passes degraded HIGH of $V_{DD} - V_{Tn}$ . NMOS turns off when source rises to $V_{DD}-V_{Tn}$ . (1)

Q9 — (b) precharge phase. Clock LOW precharges the dynamic node HIGH via PMOS; evaluation follows. (1)

Q10 — (b) energy per switching operation. $PDP = P \times t_p$ has units of energy (joules). (1)

Section B (1 mark each)

Q11 → (ii) Domino = dynamic gate + static inverter for cascading.
Q12 → (iii) Fan-out = number of driven inputs.
Q13 → (iv) $t_p$ = 50%-to-50% input/output delay.
Q14 → (v) Static power = leakage with no switching.
Q15 → (vi) PDN = NMOS to ground.
Q16 → (vii) NOR PUN = two PMOS in series.
Q17 → (viii) Rise time = 10%→90% of $V_{DD}$ .
Q18 → (i) Fan-in relates to number of inputs; remaining description (i) — activity/switching-related delay impact — is the best remaining fit for input count/complexity effect.

(Award 1 each; Q18 accept mapping to (i) as the only remaining item.)

Section C (½ T/F + 1½ justification)

Q19 — TRUE. In a stable state one of PUN/PDN is fully OFF, so no continuous $V_{DD}$ -to-ground path; ideal static power is zero (real leakage aside). (2)

Q20 — FALSE. NOR pull-up uses PMOS in series (output HIGH only when all inputs LOW); parallel PMOS is for NAND. (2)

Q21 — FALSE. Delay increases with $C_L$ : $t_p \propto C_L$ (more charge to move at fixed current). (2)

Q22 — TRUE. The parallel NMOS passes strong LOW and PMOS passes strong HIGH, giving full-swing output without $V_T$ loss. (2)

Q23 — TRUE. The output inverter makes each domino stage non-inverting; direct inverting functions require extra inversion or dual-rail. (2)

Q24 — TRUE. Dynamic energy per switch $\approx C_L V_{DD}^2$ , so lowering $V_{DD}$ reduces energy quadratically, cutting PDP (delay tradeoff noted). (2)

[
  {"claim":"NAND pull-down is 2 series NMOS: series count = 2 for a 2-input NAND",
   "code":"n_inputs=2; series_nmos=n_inputs; result = (series_nmos==2)"},
  {"claim":"NM_H = V_OH - V_IH with V_OH=1.8, V_IH=1.2 gives 0.6",
   "code":"V_OH=Rational(18,10); V_IH=Rational(12,10); NMH=V_OH-V_IH; result = (NMH==Rational(6,10))"},
  {"claim":"NMOS passes degraded high V_DD - V_Tn: 1.8-0.4=1.4",
   "code":"VDD=Rational(18,10); VTn=Rational(4,10); vhi=VDD-VTn; result = (vhi==Rational(14,10))"},
  {"claim":"Dynamic energy CV^2 halves when VDD scaled by 1/sqrt(2): ratio 0.5",
   "code":"C,V=symbols('C V',positive=True); E1=C*V**2; E2=C*(V/sqrt(2))**2; result = (simplify(E2/E1)==Rational(1,2))"}
]