CMOS inverter structure and operation

The CMOS inverter is the "hydrogen atom" of digital design: understand it fully and every other CMOS gate follows.

WHY this arrangement? (Derivation of the behaviour)

We must decide, for each input, which transistor conducts. The rules of MOS conduction:

A MOSFET conducts when $|V_{GS}| > |V_t|$ (gate-to-source voltage exceeds the threshold).

NMOS (source at GND = 0 V): $V_{GS,n} = V_{in} - 0 = V_{in}$ So NMOS is ON when $V_{in} > V_{tn}$ (input HIGH).

PMOS (source at $V_{DD}$ ): $V_{GS,p} = V_{in} - V_{DD}$ PMOS turns ON when $V_{GS,p} < V_{tp}$ (with $V_{tp}<0$ ), i.e. when $V_{in} - V_{DD} < V_{tp}$ , i.e. $V_{in}$ is low enough. So PMOS is ON when input LOW.

Case-by-case truth table

$V_{in}$	NMOS	PMOS	Output path	$V_{out}$
0 (LOW)	OFF	ON	pull-up to $V_{DD}$	$V_{DD}$ (HIGH)
$V_{DD}$ (HIGH)	ON	OFF	pull-down to GND	0 (LOW)

The Voltage Transfer Characteristic (VTC)

Five operating regions as $V_{in}$ rises:

$V_{in} < V_{tn}$ : NMOS OFF, PMOS ON (linear) → $V_{out}=V_{DD}$ .
Both ON, NMOS saturated → output starts falling.
Switching point $V_M$ : both in saturation, steep drop.
Both ON, PMOS saturated → output near GND.
$V_{in} > V_{DD}+V_{tp}$ : NMOS ON (linear), PMOS OFF → $V_{out}=0$ .

Power dissipation (WHY CMOS wins)

Dynamic (switching) power — derive it. Each time the output goes $0\to V_{DD}$ , the load capacitor $C_L$ stores energy $\tfrac12 C_L V_{DD}^2$ , and an equal amount is dissipated in the PMOS as heat. On the way down $\tfrac12 C_L V_{DD}^2$ dissipates in the NMOS. So each full cycle dissipates $C_L V_{DD}^2$ . If this happens $f$ times per second with switching probability $\alpha$ :

Static power ≈ 0 (ideal) because one transistor is always OFF, blocking the DC path. (Real chips have leakage, but classically CMOS static power is negligible.)

Noise margins (why digital is robust)

Common mistakes

Flashcards

What does "complementary" in CMOS mean?

It uses NMOS and PMOS in a matched pair that turn ON under opposite gate conditions.

In a CMOS inverter, which transistor is the pull-up and which the pull-down?

PMOS = pull-up (to

V_{DD}

), NMOS = pull-down (to GND).

When input is HIGH, which transistor conducts and what is the output?

NMOS ON, PMOS OFF → output LOW.

Why is static power ~0 in CMOS?

In steady state one transistor is always OFF, breaking the DC path from

V_{DD}

to GND.

Give the dynamic power formula and explain the

V_{DD}^2

P=\alpha C_L V_{DD}^2 f

; energy per event ∝ charge(

V_{DD}

)×voltage(

V_{DD}

What is the switching threshold

V_M

The

V_{in}

where

V_{out}=V_{in}

; both transistors saturated; ideally

V_{DD}/2

Why is PMOS made 2–3× wider than NMOS?

Hole mobility is 2–3× lower than electron mobility; widening PMOS equalizes

k_n=k_p

for symmetric VTC and equal rise/fall.

Condition for NMOS to conduct?

V_{GS,n}=V_{in}>V_{tn}

Condition for PMOS to conduct (with

V_{tp}<0

V_{in}-V_{DD}<V_{tp}

, i.e. input low enough.

What is

NM_H

NM_H=V_{OH}-V_{IH}

, the high-side noise margin.

Why does NMOS make a poor pull-up?

It passes a degraded HIGH (output only reaches

V_{DD}-V_{tn}

Recall Feynman: explain to a 12-year-old

Imagine a light bulb with two switches. One switch connects the bulb to the battery (top), the other connects it to the ground (bottom). Both switches are flipped by the same button. The trick: the switches are opposites — when one closes, the other opens. Press the button (input = 1) and the bulb-wire gets connected to ground → output = 0. Let go (input = 0) and it connects to the battery → output = 1. Because there's never a moment where both are closed for long, the battery isn't wasted — that's why your phone stays cool and its battery lasts. It always gives the opposite of the button: that's why we call it an inverter.

Connections

CMOS logic gates (NAND NOR) — built by series/parallel networks of these two devices.
MOSFET operating regions — cutoff/triode/saturation used in the VTC derivation.
Dynamic power and clock frequency — the $\alpha C_L V_{DD}^2 f$ scaling.
Propagation delay and transistor sizing — why $k_n=k_p$ balances rise/fall.
Noise margins in digital logic — full-rail swing advantage.
Leakage and short-channel effects — where "static power ≈ 0" breaks down in modern nodes.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, CMOS inverter basically do switch hain jo series mein lage hain — upar PMOS (pull-up, jo output ko $V_{DD}$ se jodta hai) aur neeche NMOS (pull-down, jo output ko ground se jodta hai). Dono ka gate ek hi input se juda hai, lekin dono opposite behave karte hain: NMOS tab ON hota hai jab input HIGH ho, aur PMOS tab ON hota hai jab input LOW ho. Isliye output hamesha input ka ulta aata hai — yahi to inverter (NOT gate) ka kaam hai.

Sabse important baat: steady state mein koi ek transistor hamesha OFF rehta hai, matlab $V_{DD}$ se ground tak koi seedha rasta nahi banta, to static current lagbhag zero. Yahi wajah hai ki CMOS itna kam power khaata hai aur mobile chips isi pe bane hain. Power sirf switching ke time lagti hai — formula $P=\alpha C_L V_{DD}^2 f$ . Dhyan do $V_{DD}^2$ pe: supply voltage thoda kam karo, power bahut zyada kam ho jaati hai.

Ek aur practical point: PMOS ko NMOS se lagbhag 2–3 guna chauda (wide) banate hain, kyunki holes electrons se dheere chalte hain. Isse pull-up aur pull-down barabar strong ho jaate hain, switching point $V_M$ theek $V_{DD}/2$ pe aata hai, aur rise-time = fall-time. Yaad rakho: "P likes 0, N likes 1" — NMOS strong 0 pass karta hai, PMOS strong 1, isiliye placement isi hisaab se hoti hai.

The Big Picture

What is it made of?

WHY this arrangement? (Derivation of the behaviour)

Case-by-case truth table

The Voltage Transfer Characteristic (VTC)

Power dissipation (WHY CMOS wins)

Noise margins (why digital is robust)

Common mistakes

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — CMOS Circuit Design

Connections